// Verilog HDL for "Multifier", "Multifier" "functional"
module Multifier(A,B,ALU) ;
//definition of the ports
input [7:0] A,B;
output [15:0] ALU;
wire [15:0] result;
parameter give0 = 8'b00000000; //10
//definition of connection
assign result = multify0(A,B)+multify1(A,B)+multify2(A,B)+multify3(A,B)+multify4(A,B)+multify5(A,B)+multify6(A,B)+multify7(A,B);
assign ALU = result;
//definition of function,multify0
function [15:0] multify0;
input [7:0] A,B; //20
if( B[0]==1 ) multify0 = { give0[7:0] , A[7:0] };
else multify0 = { give0[7:0] , give0[7:0] };
endfunction
//definition of function,multify1
function [15:0] multify1;
input [7:0] A,B;
if( B[1]==1 ) multify1 = { give0[7:1] , A[7:0] , give0[0] };
else multify1 = { give0[7:0] , give0[7:0] }; //30
endfunction
//definition of function,multify2
function [15:0] multify2;
input [7:0] A,B;
if( B[2]==1 ) multify2 = { give0[7:2] , A[7:0] , give0[1:0] };
else multify2 = { give0[7:0] , give0[7:0] };
endfunction
//40
//definition of function,multify3
function [15:0] multify3;
input [7:0] A,B;
if( B[3]==1 ) multify3 = { give0[7:3] , A[7:0] , give0[2:0] };
else multify3 = { give0[7:0] , give0[7:0] };
endfunction
//definition of function,multify4
//50
function [15:0] multify4;
input [7:0] A,B;
if( B[4]==1 ) multify4 = { give0[7:4] , A[7:0] , give0[3:0] };
else multify4 = { give0[7:0] , give0[7:0] };
endfunction
//definition of function,multify5
function [15:0] multify5;
input [7:0] A,B; //60
if( B[5]==1 ) multify5 = { give0[7:5] , A[7:0] , give0[4:0] };
else multify5 = { give0[7:0] , give0[7:0] };
endfunction
//definition of function,multify6
function [15:0] multify6;
input [7:0] A,B;
if( B[6]==1 ) multify6 = { give0[7:6] , A[7:0] , give0[5:0] };
else multify6 = { give0[7:0] , give0[7:0] }; //70
endfunction
//definition of function,multify7
function [15:0] multify7;
input [7:0] A,B;
if( B[7]==1 ) multify7 = { give0[7] , A[7:0] , give0[6:0] };
else multify7 = { give0[7:0] , give0[7:0] };
endfunction
endmodule