8.1. Write functions qit2bit and bit2qit for converting an unconstrained qit_vector to a BIR_VECTOR, and an unconstrained BIT_VECTOR to a qit_vector, respectively. Take advantage of arrays with noninteger indices for converting from one base type to another.

8.2. Use a selected signal assignment to describe a BCD seven-segment decoder. Use qit as the base type of all elements of inputs and outputs. You may use the functions you created in Problem 8.1.

8.3. Write a description for an 8-to-1 multiplexer with a 3-bit decoded input in the qit logic value system. Take advantage of the functions you prepared in Problem 8.1.

8.4. Wire the multiplexer in Figure 8.5 and the decoder of Figure 8.8 to generate a multiplexer with decoded input.

8.5. A decoder with an enable input is easily cascadable. Write a VHDL description for a 3-to-8 decoder with an active low enable input and an active high enable input. When disabled, all outputs have to be 0. Use the qit logic value system.

8.6. Write a VHDL description for wiring two of the decoders in Problem 8.5 to implement a 4-to-16 decoder.

8.7. Use guarded signal assignments to describe a simple latch with q and NOT q outputs that functions the same as a latch formed by cross-coupled NOR gates with clocked inputs. Use reasonable delay values.

8.8. Use two of the latches in Problem 8.7 and necessary logic operations to describe a master-slave JK flip-flop.

8.9. Use guarded block statements to describe an 8-bit shift register. The structure has a serial input for right shifting the data and a single serial output. All activities are synchronized with the leading edge of the clock.

8.10. Write a description for a universal 8-bit shift register with a 2-bit mode select input, an 8-bit parallel data input, and an 8-bit data output. The unit performs a right shift if the mode is 01, left shift if the mode is 10, and a parallel load of the eight bit input if the mode is 11. All activities are synchronized with the leading edge of the clock.

8.11. Write a description for a clocked T-type flip-flop. If T is '1' on the rising edge of the clock, the outputs of the flip-flop toggle. Use the qit logic value system.

8.12. Write a VHDL description for a rising edge trigger D-type flip-flop with asynchronous set and reset inputs and two outputs. Label the data, clock, set and reset inputs d, c, s and r, respectively. Active s or r inputs override the clocked values on the d input; s and r cannot simultaneously be active. Changes on d without the rising edge of c have no effect on the q and qb outputs of the flip-flop. Use delay parameters sq_delay, rq_delay, and cq_delay for setting, resetting, and clocking the flip-flop, respectively. Develop a test bench for testing this flip-flop. Generate a simple periodic clock using a conditional signal assignment.

8.13. Given the following description, show waveforms on x1, x2 and diff in a timing diagram. Explain the reason for different waveforms on x1 and x2.

8.14. A resolution function, named majority, resolves to the majority of '1's or '0's on its inputs. If there are more ones ('1's) than zeros, the function generates a '1' output. If there are more zeros ('0's) than ones, the function generates a '0' output. If the number of '1's and '0's are equal the output will be 'E'. A) Declare all necessary types, and write the description of the majority function. B) Declare types and subtypes that can be used for declaring signals that can take advantage of this resolution function. C) Package all of the above, and show how a single-bit signal candidate and a 16-bit signal candidate_16 should be declared such that placement of multiple values on these signals will resolve according to the majority function.

8.15. A resolution function, named all_same, resolves all '1's on its sources to '1' and all '0's to zero. This function generates 'E', indicating an error condition if conflicting values are placed at its sources. A) Declare all necessary types, and write the description of the all_same function. B) Declare types and subtypes that can be used for declaring signals that can take advantage of this resolution function. C) Package all of the above, and show how a single-bit signal x and a 16-bit signal x16 should be declared such that placement of multiple values on these signals will resolve according to the all_same function. D) What actual hardware construct behaves like the all_same function?

8.16. Ten controlled sources (s(i) where i is 1 to 10) that range between -25 and +25 volts are connected to the sources of 10 parallel MOS transistors. The common drain of these transistors is node n. Each sources, s(i), is controlled by a control line, c(i), that is connected to the gate of the MOS transistors. Control line voltage also range between -25 to +25. A control line, c(i), turns its corresponding transistor on, i.e., causes it to conduct which in turn causes node n be driven by source s(i) when c(i) is greater than or equal to +5 volts. The on-resistance of the parallel transistors is 10 KW . Node n is also connected to a 25 V supply through a 10 KW pull-up resistor. At any time, any number of controlled sources may be active. A) Write a resolution function that returns the voltage at node n depending on the value and number of active sources. B) In a test architecture, declared a resolved guarded signal (node n) whose resolution function is that in Part A. Use guarded block statements to conditionally drive this signal (node n) with up to 10 sources, each of which can take a value between -25 and +25. This is analogous to connecting 10 parallel MOS transistors to node n and applying various voltages to the sources of these transistors. Use a generate statement instead of 10 individual block statements.

8.17. Use a block statement, a resolution function, a conditional signal assignment, and a disconnection specification to model a tri-state noninverting buffer. The gate has data and enable inputs x and e, and output z. When e is ‘1’, the z output is driven by x; otherwise, the output is in the high impedance state. The inputs and outputs are of type qit and output is a guarded signal. Use the three delay values tp_e_z_float, tp_x_z_high, and tp_x_z_low where: tp_e_z_float is for e changing to ‘0’ and causing the output to disconnect from the input; tp_x_z_high is for e equal to ‘1’ and x changing to ‘1’ causing the output to become ‘1’, or when x is ‘1’ and e changes to ‘1’; and tp_x_z_low is for e equal to ‘1’ and x changing to ‘0’ causing the output to become ‘0’, or when x is ‘0’ and e changes to ‘1’. Use ‘0’ and ‘1’ values for the inputs, and map ‘X’ and ‘Z’ into ‘0’ and ‘1’, respectively. Use two such buffers for implementing a 2-to-1 multiplexer.

8.18. Design a Mealy sequence detector and develop a tester for this circuit. The circuit monitors its x input for the 10110 sequence. When this sequence is found, the z output becomes '1'. A valid data bit is one that coincides with the rising edge of the clock, c. Make sure that you understand the behavior of a Mealy machine output. A) Write a VHDL dataflow description for this sequence detector. B) Show a test bench that tests this circuit for the 10110110101 sequence on the x input. Use a periodic clock.

8.19. Accurately model the circuit shown below in VHDL at the dataflow level. This circuit uses positive edge triggered D flip-flop. Flip-flop 1 has an asynchronous reset in addition to the synchronous D input. The reset input has priority over the clock input. Write a complete VHDL description at the dataflow level for modeling this circuit. Your description should include an ENTITY and an ARCHITECTURE.

8.20. Write the complete VHDL description for a Moore machine detecting 10111 or 11001. The circuit continuously monitors its x input. When in five consecutive clock pulses either sequence is found, the z output becomes '1' and stays at this level for a complete clock pulse. Write a VHDL dataflow description for this sequence detector. Show a test bench that tests this circuit for the 1011001011100110100 sequence on the x input. Use a periodic clock.

8.21. Write the complete VHDL description for a circuit with an input x and two outputs, z1 and z2. The circuit consists of two concurrent Mealy machines. The z1 output becomes '1' when a 1011 sequence is found on the input, and the z2 output becomes '1' when a 110 sequence is found x. Your description should be capable of having multiple active states.

8.22. Write a VHDL description for a Moore state machine with resetting capability. While continuously searching for 1011 on the data input x, if the reset input, r, becomes '1', the circuit returns to a reset state. In this state, all previously received data will be ignored and a complete 1011 is required before the output becomes '1'. While not reset, circuit responds to overlapping valid sequences.

8.23. Describe a synchronous shifter circuit with a left serial input, lsi, and an 8-bit shift register. The circuit synchronously resets when a ‘1’ appears on its reset input. After a reset, for every five clock pulses, a data bit from the lsi input is shifted into the 8-bit register. You may use utilities of the basic_utilities package.

8.24. Rewrite the description of the generic state machine of Section 8.2.4 such that the output table, the next state table, and its initial state are specified through generics. Instantiate this description on test for the same tables specified in Section 8.2.4.

8.25. Configure the state machine of Problem 8.24 for a 11011 or 10110 moore detector. Allow overlapping sequences. Generate appropriate next-state and output tables. Instantiate this machine and test it for several test sequences.