ENTITY inv IS
PORT (i1 : IN BIT; o1 : OUT BIT);
END inv;
(b)
ARCHITECTURE single_delay OF inv IS
BEGIN
o1 <= NOT i1 AFTER 4 NS;
END single_delay;
(c)
FIGURE 5.1
Inverter (a) symbol, (b) entity declaration, (c) architecture body, (d) notation.
FIGURE 5.2
Details of the entity declaration of inverter.
FIGURE 5.3
Elements of aspect notation.
FIGURE 5.4
Using ports (a) Inputs, (b) Outputs, (c) Bi-directional ports, (d) Buffers.
ENTITY nand2 IS
PORT (i1, i2 : IN BIT; o1 : OUT BIT);
END nand2;
(b)
ARCHITECTURE single_delay OF nand2 IS
BEGIN
o1 <= i1 NAND i2 AFTER 5 NS;
END single_delay;
(c)
FIGURE 5.5
Two-input NAND (a) symbol, (b) entity declaration, (c) architecture body, (d) notation.
FIGURE 5.6
Port clause details for nand2.
ENTITY nand3 IS
PORT (i1, i2, i3 : IN BIT; o1 : OUT BIT);
END nand3;
(b)
ARCHITECTURE single_delay OF nand3 IS
BEGIN
o1 <= NOT ( i1 AND i2 AND i3 ) AFTER 6 NS;
END single_delay;
(c)
FIGURE 5.7
Three-input NAND (a) symbol, (b) entity declaration, (c) architecture body, (d) notation.
FIGURE 5.8
Logical symbol of a single bit comparator.
FIGURE 5.9
Karnaugh maps for the outputs of the single bit comparator.
FIGURE 5.10
Logical diagram of bit_comparator.
(a)
ENTITY bit_comparator IS
PORT (a, b, -- data inputs
gt, -- previous greater than
eq, -- previous equal
lt : IN BIT; -- previous less than
a_gt_b, -- greater
a_eq_b, -- equal
a_lt_b : OUT BIT); -- less than
END bit_comparator;
(b)
FIGURE 5.11
Interface description of bit_comparator, (a) interface aspect, (b) entity declaration.
FIGURE 5.12
Composition Aspect of bit_comparator.
ARCHITECTURE gate_level OF bit_comparator IS
COMPONENT n1 PORT (i1: IN BIT; o1: OUT BIT); END COMPONENT;
COMPONENT n2 PORT (i1, i2: IN BIT; o1: OUT BIT); END COMPONENT;
COMPONENT n3 PORT (i1, i2, i3: IN BIT; o1: OUT BIT);
END COMPONENT;
FOR ALL : n1 USE ENTITY WORK.inv (single_delay);
FOR ALL : n2 USE ENTITY WORK.nand2 (single_delay);
FOR ALL : n3 USE ENTITY WORK.nand3 (single_delay);
-- Intermediate signals
SIGNAL im1,im2, im3, im4, im5, im6, im7, im8, im9, im10 : BIT;
BEGIN
-- a_gt_b output
g0 : n1 PORT MAP (a, im1);
g1 : n1 PORT MAP (b, im2);
g2 : n2 PORT MAP (a, im2, im3);
g3 : n2 PORT MAP (a, gt, im4);
g4 : n2 PORT MAP (im2, gt, im5);
g5 : n3 PORT MAP (im3, im4, im5, a_gt_b);
-- a_eq_b output
g6 : n3 PORT MAP (im1, im2, eq, im6);
g7 : n3 PORT MAP (a, b, eq, im7);
g8 : n2 PORT MAP (im6, im7, a_eq_b);
-- a_lt_b output
g9 : n2 PORT MAP (im1, b, im8);
g10 : n2 PORT MAP (im1, lt, im9);
g11 : n2 PORT MAP (b, lt, im10);
g12 : n3 PORT MAP (im8, im9, im10, a_lt_b);
END gate_level;
FIGURE 5.13
Architecture body of bit_comparator identified as gate_level.
FIGURE 5.14
Syntax details of the architecture body of bit_comparator.
FIGURE 5.15
Component instantiation statement syntax details.
ARCHITECTURE netlist OF bit_comparator IS
-- Intermediate signals
SIGNAL im1,im2, im3, im4, im5, im6, im7, im8, im9, im10 : BIT;
BEGIN
-- a_gt_b output
g0 : ENTITY WORK.inv(single_delay) PORT MAP (a, im1);
g1 : ENTITY WORK.inv(single_delay) PORT MAP (b, im2);
g2 : ENTITY WORK.nand2(single_delay) PORT MAP (a, im2, im3);
g3 : ENTITY WORK.nand2(single_delay) PORT MAP (a, gt, im4);
g4 : ENTITY WORK.nand2(single_delay) PORT MAP (im2, gt, im5);
g5 : ENTITY WORK.nand3(single_delay) PORT MAP (im3, im4, im5, a_gt_b);
-- a_eq_b output
g6 : ENTITY WORK.nand3(single_delay) PORT MAP (im1, im2, eq, im6);
g7 : ENTITY WORK.nand3(single_delay) PORT MAP (a, b, eq, im7);
g8 : ENTITY WORK.nand2(single_delay) PORT MAP (im6, im7, a_eq_b);
-- a_lt_b output
g9 : ENTITY WORK.nand2(single_delay) PORT MAP (im1, b, im8);
g10 : ENTITY WORK.nand2(single_delay) PORT MAP (im1, lt, im9);
g11 : ENTITY WORK.nand2(single_delay) PORT MAP (b, lt, im10);
g12 : ENTITY WORK.nand3(single_delay) PORT MAP (im8, im9, im10, a_lt_b);
END netlist;
FIGURE 5.16
Netlist description of bit_comparator.
FIGURE 5.17
bit_comparator simulation run.
FIGURE 5.18
Logical symbol of a 4-bit comparator.
FIGURE 5.19
A 4-bit comparator using four single bit comparators.
(a)
ENTITY nibble_comparator IS
PORT (a, b : IN BIT_VECTOR (3 DOWNTO 0); -- a and b data inputs
gt, -- previous greater than
eq, -- previous equal
lt : IN BIT; -- previous less than
a_gt_b, -- a > b
a_eq_b, -- a = b
a_lt_b : OUT BIT); -- a < b
END nibble_comparator;
FIGURE 5.20
Interface description of nibble_comparator, (a) interface aspect, (b) entity declaration.
FIGURE 5.21
Composition aspect of nibble_comparator.
ARCHITECTURE iterative OF nibble_comparator IS
COMPONENT comp1
PORT (a, b, gt, eq, lt : IN BIT; a_gt_b, a_eq_b, a_lt_b : OUT BIT);
END COMPONENT;
FOR ALL : comp1 USE ENTITY WORK.bit_comparator (gate_level);
SIGNAL im : BIT_VECTOR ( 0 TO 8);
BEGIN
c0: comp1 PORT MAP (a(0), b(0), gt, eq, lt, im(0), im(1), im(2));
c1to2: FOR i IN 1 TO 2 GENERATE
c: comp1 PORT MAP (a(i), b(i), im(i*3-3), im(i*3-2), im(i*3-1),
im(i*3+0), im(i*3+1), im(i*3+2) );
END GENERATE;
c3: comp1
PORT MAP (a(3), b(3), im(6), im(7), im(8), a_gt_b, a_eq_b, a_lt_b);
END iterative;
FIGURE 5.22
Iterative architecture of nibble_comparator.
FIGURE 5.23
Association list of c instance of comp1 within generate statement.
FIGURE 5.24
Generate statement syntax details.
ARCHITECTURE iterative OF nibble_comparator IS
COMPONENT comp1
PORT (a, b, gt, eq, lt : IN BIT; a_gt_b, a_eq_b, a_lt_b : OUT BIT);
END COMPONENT;
FOR ALL : comp1 USE ENTITY WORK.bit_comparator (gate_level);
CONSTANT n : INTEGER := 4;
SIGNAL im : BIT_VECTOR ( 0 TO (n-1)*3-1);
BEGIN
c_all: FOR i IN 0 TO n-1 GENERATE
l: IF i = 0 GENERATE
least: comp1 PORT MAP (a(i), b(i), gt, eq, lt, im(0), im(1), im(2) );
END GENERATE;
m: IF i = n-1 GENERATE
most: comp1 PORT MAP (a(i), b(i),
im(i*3-3), im(i*3-2), im(i*3-1), a_gt_b, a_eq_b, a_lt_b);
END GENERATE;
r: IF i > 0 AND i < n-1 GENERATE
rest: comp1 PORT MAP (a(i), b(i), im(i*3-3), im(i*3-2), im(i*3-1),
im(i*3+0), im(i*3+1), im(i*3+2) );
END GENERATE;
END GENERATE;
END iterative;
FIGURE 5.25
A more flexible iterative architecture of nibble_comparator.
l: IF i = 0 GENERATE
FOR least : comp1 USE ENTITY WORK.bit_comparator (gate_level);
BEGIN
least: comp1 PORT MAP (a(i), b(i), gt, eq, lt, im(0), im(1), im(2) );
END GENERATE;
VHDL 93, Unambigious Configuration Specification
FIGURE 5.26
A test bench for nibble_comparator, the composition aspect.
ENTITY nibble_comparator_test_bench IS
END nibble_comparator_test_bench ;
--
ARCHITECTURE input_output OF nibble_comparator_test_bench IS
COMPONENT comp4 PORT (a, b : IN bit_vector (3 DOWNTO 0);
a_gt_b, a_eq_b, a_lt_b : IN BIT;
a_gt_b_out, a_eq_b_out, a_lt_b_out : OUT BIT);
END COMPONENT;
FOR a1 : comp4 USE ENTITY WORK.nibble_comparator(iterative);
SIGNAL a, b : BIT_VECTOR (3 DOWNTO 0);
SIGNAL eql, lss, gtr : BIT;
SIGNAL vdd : BIT := '1';
SIGNAL gnd : BIT := '0';
BEGIN
a1: comp4 PORT MAP (a, b, gnd, vdd, gnd, gtr, eql, lss);
a2: a <= "0000", ---- a = b (steady state)
"1111" AFTER 0500 NS, -- a > b (worst case)
"1110" AFTER 1500 NS, -- a < b (worst case)
"1110" AFTER 2500 NS, -- a > b (need bit 1 info)
"1010" AFTER 3500 NS, -- a < b (need bit 2 info)
"0000" AFTER 4000 NS, -- a < b (steady state, prepare for next)
"1111" AFTER 4500 NS, -- a = b (worst case)
"0000" AFTER 5000 NS, -- a < b (need bit 3 only, best case)
"0000" AFTER 5500 NS, -- a = b (worst case)
"1111" AFTER 6000 NS; -- a > b (need bit 3 only, best case)
a3 : b <= "0000", ---- a = b (steady state)
"1110" AFTER 0500 NS, -- a > b (worst case)
"1111" AFTER 1500 NS, -- a < b (worst case)
"1100" AFTER 2500 NS, -- a > b (need bit 1 info)
"1100" AFTER 3500 NS, -- a < b (need bit 2 info)
"1111" AFTER 4000 NS, -- a < b (steady state, prepare for next)
"1111" AFTER 4500 NS, -- a = b (worst case)
"1111" AFTER 5000 NS, -- a < b (need bit 3 only, best case)
"0000" AFTER 5500 NS, -- a = b (worst case)
"0000" AFTER 6000 NS; -- a > b (need bit 3 only, best case)
END input_output;
FIGURE 5.27
Test bench for iterative architecture of nibble_comparator.
|
TIME (NS) |
SIGNALS |
||||
|
a(3:0) |
b(3:0) |
gtr |
eql |
lss |
|
|
0 |
"0000" |
"0000" |
'0' |
'0' |
'0' |
|
5 |
...... |
...... |
... |
'1' |
... |
|
500 |
"1111" |
"1110" |
... |
... |
... |
|
544 |
...... |
...... |
'1' |
... |
... |
|
548 |
...... |
...... |
... |
'0' |
... |
|
1500 |
"1110" |
"1111" |
... |
... |
... |
|
1544 |
...... |
...... |
'0' |
... |
... |
|
1548 |
...... |
...... |
... |
... |
'1' |
|
2500 |
...... |
"1100" |
... |
... |
... |
|
2533 |
...... |
...... |
... |
... |
'0' |
|
2537 |
...... |
...... |
'1' |
... |
... |
|
3500 |
"1010" |
...... |
... |
... |
... |
|
3522 |
...... |
...... |
'0' |
... |
... |
|
3526 |
...... |
...... |
... |
... |
'1' |
|
4000 |
"0000" |
"1111" |
... |
... |
... |
|
4500 |
"1111" |
...... |
... |
... |
... |
|
4544 |
...... |
...... |
... |
'1' |
... |
|
4548 |
...... |
...... |
... |
... |
'0' |
|
5000 |
"0000" |
...... |
... |
... |
... |
|
5011 |
...... |
...... |
... |
'0' |
... |
|
5015 |
...... |
...... |
... |
... |
'1' |
|
5500 |
...... |
"0000" |
... |
... |
... |
|
5544 |
...... |
...... |
... |
... |
'0' |
|
5548 |
...... |
...... |
... |
'1' |
... |
|
6000 |
"1111" |
...... |
... |
... |
... |
|
6011 |
...... |
...... |
'1' |
... |
... |
|
6015 |
...... |
...... |
... |
'0' |
... |
FIGURE 5.28
Simulation report for simulating the test bench in Figure 5.27. All events are observed.
FIGURE 5.29
Logical diagram of a simple latch.
ENTITY sr_latch IS PORT (s, r, c : IN BIT; q : OUT BIT);
END sr_latch;
--
ARCHITECTURE gate_level OF sr_latch IS
COMPONENT n2 PORT (i1, i2: IN BIT; o1: OUT BIT); END COMPONENT;
FOR ALL : n2 USE ENTITY WORK.nand2 (single_delay);
SIGNAL im1, im2, im3, im4 : BIT;
BEGIN
g1 : n2 PORT MAP (s, c, im1);
g2 : n2 PORT MAP (r, c, im2);
g3 : n2 PORT MAP (im1, im4, im3);
g4 : n2 PORT MAP (im3, im2, im4);
q <= im3;
END gate_level;
FIGURE 5.30
VHDL description of set-reset latch.
ARCHITECTURE gate_level OF sr_latch IS
COMPONENT n2 PORT (i1, i2: IN BIT; o1: BUFFER BIT); END COMPONENT;
FOR ALL : n2 USE ENTITY WORK.nand2 (single_delay);
SIGNAL im1, im2, im4 : BIT;
BEGIN
g1 : n2 PORT MAP (s, c, im1);
g2 : n2 PORT MAP (r, c, im2);
g3 : n2 PORT MAP (im1, im4, q);
g4 : n2 PORT MAP (q, im2, im4);
END gate_level;
FIGURE 5.31
sr_latch (gate_level) architecture using BUFFER.
ARCHITECTURE fast_single_delay OF nand2 IS
BEGIN
o1 <= i1 NAND i2 AFTER 3 NS;
END fast_single_delay;
FIGURE 5.32
A faster NAND gate.
(a)
ARCHITECTURE gate_level OF sr_latch IS
COMPONENT n2 PORT (i1, i2: IN BIT; o1: OUT BIT); END COMPONENT;
FOR g1, g3 : n2 USE ENTITY WORK.nand2 (fast_single_delay);
FOR g2, g4 : n2 USE ENTITY WORK.nand2 (single_delay);
SIGNAL im1, im2, im3, im4 : BIT;
BEGIN
g1 : n2 PORT MAP (s, c, im1);
g2 : n2 PORT MAP (r, c, im2);
g3 : n2 PORT MAP (im1, im4, im3);
g4 : n2 PORT MAP (im3, im2, im4);
q <= im3;
END gate_level;
FIGURE 5.33
SR-latch, using gates with different delays, (a) composition aspect, (b) architecture body.
(a)
ARCHITECTURE gate_level OF sr_latch IS
COMPONENT n2 PORT (x, y: IN BIT; z: OUT BIT); END COMPONENT;
FOR g1, g3 : n2 USE ENTITY WORK.nand2 (single_delay) PORT MAP (x, y, z);
FOR g2, g4 : n2 USE ENTITY WORK.nand3 (single_delay) PORT MAP (x, x, y, z);
SIGNAL im1, im2, im3, im4 : BIT;
BEGIN
g1 : n2 PORT MAP (s, c, im1);
g2 : n2 PORT MAP (r, c, im2);
g3 : n2 PORT MAP (im1, im4, im3);
g4 : n2 PORT MAP (im3, im2, im4);
q <= im3;
END gate_level;
FIGURE 5.34
SR-latch, using nand2 and nand3 gates, (a) composition aspect, (b) architecture body.
FIGURE 5.35
Two-step association.
FIGURE 5.36
Configuration specification syntax details.
FIGURE 5.37
Composition aspect of old_new_comparator.
ENTITY old_new_comparator IS
PORT (i : IN BIT_VECTOR (7 DOWNTO 0);
clk : IN BIT; gt_compare, eq_compare : OUT BIT);
END old_new_comparator;
--
ARCHITECTURE wiring OF old_new_comparator IS
COMPONENT byte_latch
PORT (di : IN BIT_VECTOR (7 DOWNTO 0);
clk : IN BIT; qo : OUT BIT_VECTOR (7 DOWNTO 0));
END COMPONENT;
COMPONENT byte_comparator
PORT(a, b : BIT_VECTOR (7 DOWNTO 0);
gt, eq, lt : IN BIT; a_gt_b, a_eq_b, a_lt_b : OUT BIT);
END COMPONENT;
SIGNAL con1 : BIT_VECTOR (7 DOWNTO 0);
SIGNAL vdd : BIT := '1'; SIGNAL gnd : BIT := '0';
BEGIN
l : byte_latch PORT MAP(i, clk, con1);
c : byte_comparator
PORT MAP(con1, i, gnd, vdd, gnd, gt_compare, eq_compare, OPEN);
END wiring;
FIGURE 5.38
old_new_comparator VHDL description.
ENTITY byte_latch IS
PORT (di : IN BIT_VECTOR (7 DOWNTO 0);
clk : IN BIT; qo : OUT BIT_VECTOR( 7 DOWNTO 0));
END byte_latch;
--
ARCHITECTURE iterative OF byte_latch IS
COMPONENT d_latch
PORT (d, c : IN BIT; q : OUT BIT);
END COMPONENT;
BEGIN
g : FOR i IN di'RANGE GENERATE
l7dt0 : d_latch PORT MAP (di(i), clk, qo(i));
END GENERATE;
END iterative;
FIGURE 5.39
VHDL description of byte_latch.
(a)
ENTITY d_latch IS PORT(d,c : IN BIT;q: OUT BIT); END d_latch;
--
ARCHITECTURE sr_based OF d_latch IS
COMPONENT sr_latch PORT (s, r, c : IN BIT; q : OUT BIT);
END COMPONENT;
COMPONENT inv PORT (i1 : IN BIT; o1 : OUT BIT);
END COMPONENT;
SIGNAL dbar: BIT;
BEGIN
c1 : sr_latch PORT MAP (d, dbar, c, q);
c2 : inv PORT MAP (d, dbar);
END sr_based;
(b)
FIGURE 5.40
Design of d_latch (a) Composition (b) VHDL description.
ARCHITECTURE iterative OF nibble_comparator IS
COMPONENT bit_comparator
PORT (a, b, gt, eq, lt : IN BIT; a_gt_b, a_eq_b, a_lt_b : OUT BIT);
END COMPONENT;
CONSTANT n : INTEGER := 8;
SIGNAL im : BIT_VECTOR ( 0 TO (n-1)*3-1);
BEGIN
c_all: FOR i IN 0 TO n-1 GENERATE
l: IF i = 0 GENERATE
least: bit_comparator PORT MAP (a(i), b(i), gt, eq, lt, im(0), im(1), im(2) );
END GENERATE;
m: IF i = n-1 GENERATE
most: bit_comparator PORT MAP (a(i), b(i),
im(i*3-3), im(i*3-2), im(i*3-1), a_gt_b, a_eq_b, a_lt_b);
END GENERATE;
r: IF i > 0 AND i < n-1 GENERATE
rest: bit_comparator PORT MAP (a(i), b(i), im(i*3-3), im(i*3-2), im(i*3-1),
im(i*3+0), im(i*3+1), im(i*3+2) );
END GENERATE;
END GENERATE;
END iterative;
FIGURE 5.41
Byte comparator VHDL description.