EE295 - ASIC Design Using VHDL - Class 9

Configuration

Assignment: Read Ch 7

Outline:

• Configuration
• The Default Configuration
• Configuring
  • Components
  • Ports
  • Generics in
    • Default Specification
    • Component Instantiation
    • Configuration
  • Blocks
  • Architectures
• Board-Socket-Chip Analogy

Configuration

• In a Hierarchical Design Environment
• Need to Control Design Integrity
• Need a Way to Specify How to Build the Desired Design

Default ( Simple ) Configuration

• Circumstances:
  • 1 Entity - 1 Architecture
  • Architecture is Entirely Self-Contained
  • ie. No External References, No Components
  • No Ambiguity
• Syntax:
  • Configuration config_name of entity_name is
    • for architecture_name
    • end for;
  • end config_name;

Configuring Components

Syntax:

• Configuration config_name of entity_name is
  • for architecture_name
    • for comp_label:comp_name Use
    • for others:comp_name Use
    • -or-
    • for all:comp_name Use
      • Entitylibrary_name.entity_name(architecture_name);
    • end for;
  • end for;
• end config_name;

Lower-Level Configurations

Assuming a VHDL Library Called library_name representing an ASIC Logic Library of Cells Consisting of Syntax:

• Entity entity_name
• Architecturearchitecture_name of entity_name
• Configurationlower_config_name of entity_name (Default)

Then a Designer Using this Library Can Bind Those Cell Instances Using

• Declare/Instantiate a Component and Configure it
• Configuration config_name of entity_name is
  • for architecture_name
    • for comp_label:comp_name Use
    • for others:comp_name Use
    • -or-
    • for all:comp_name Use
      • Configurationlibrary_name.lower_config_name;
    • end for;
  • end for;
• end config_name;

Configuring Ports

We have specified how a component binds to an Entity where the ports match. If they don't additional information is required.. Syntax:

• Configuration config_name of entity_name is
  • for architecture_name
    • for comp_label:comp_name Use
      • Entitylibrary_name.entity_name[(architecture_name)]
      • Configurationlibrary_name.lower_config_name;
        • port map ( comp_port => entity_port, ...);
        • port map ( formal => actual, ...);
    • end for;
  • end for;
• end config_name;

Configuring Generics

Generics Provides a Means of Passing Information Into an Entity. In Some Cases, That Information Needs to be Provided as Feedback From Downstream Design Tools - Back Annotation. With This In Mind Configuration May be Used to Specify Generic Values. Syntax:

• Generics May Have a Default Value as Part of Their Declaration
  • entity ent_name is
    • generic ( cell_name : array (0 to 31) of char; delay : time := 1.0 nS; ... );
    • --delay has a default value
    • port ( ..);
  • end ent_name;
• Generics May Be Specified in a Component Instance
  • In the Architecture's Declarative Region..
  • Component comp_name
    • generic ( delay : time; .. );
    • port ( .. );
  • end component;
  • In the Architecture's Body..
  • U1:comp_name
    • generic map ( delay => 1.1 nS )
    • port map ( .. );
• Generics May Be Specified in a Configuration
  • Configuration config_name of entity_name is
    • for architecture_name
      • for U1:comp_name Use
        • Entitylibrary_name.entity_name[(architecture_name)]
          • generic map ( delay => 1.3 nS );
      • end for;
    • end for;
  • end config_name;
  • Note - Updating Default Values and Architectures Containing Component Instances Require Editing & Complete Re-Compile of Designs. Computationally Expensive!!
  • Configurations Allow Updates to Generic Values in the Most Efficient Manner.

Block Configurations

A Design Architecture Divided Into Blocks Requires Specification of the Block Region.

• Configuration config_name of entity_name is
  • for architecture_name
    • for block_name
      • for U1:comp_name Use
        • Entitylibrary_name.entity_name[(architecture_name)]
          • generic map ( delay => 1.3 nS );
      • end for;
    • end for;
  • end for;
• end config_name;

Architecture Configurations

• Simplest Form of Configuration For Small, Simple Designs
• Appears in Architecture's Declarative Region
• Component comp_name
• ..
• For all|comp_label|others :comp_name USE Configuration|Entity Specification

Board-Socket-Chip Analogy