EE295 - ASIC Design Using VHDL

Data Types

Assignment:

• Assignment: Read Ch 4
• Examine the ROM Function Described on Pg 84. Try a few input/output values.
• Explain what the function is doing. What 'conversion' function is it emulating?

 VHDL borrows from the structured programming technique of utilizing
data types for both the  sequential and behavioral sides of the language.
The full range of types found in such popular programming
languages as C or Pascal is available as well as some electrically
significant ones. Often novice designers find 'type mismatch' errors
in seemingly intuitive assignment statements or expression evaluations.
On the plus side, the use of data types can be a powerful means of
design expression. Remember..

• VHDL is a strongly 'typed' language
• Understanding and utilizing types is important

Outline:

• Data Objects
• Scoping Rules
• Variable
• Constant
• Predefined Data Type
• Enumerated Type
• Physical Type
• Composite Types
  • Array
  • Record
• Access Type
• File Type
• Sub Types

Data Objects..

• Signal - Electrical Interconnection of all Objects
  • Appears in any Legal Declarative Region
  • Signal sig1 [, sig2, sig3...] : signal_type := initial_value;
• Variable - Storage of Temporary, Local Information Variable ..
• Constant - Convenient representation of permanent information constant ..

Signals: Rules of Scope

• Entities, architectures and packages all have declarative regions.
• Signals declared in an architecture are visible only in that architecture
• Signals declared in an entity are visible in all of the architecures of that entity
• Signals declared in a package are visible in any entity/architecture that declares it's dependence on that package

Variables

• Variable Assignment Inherently More Efficient Than Signal Evaluation
  • Signals Require a Driver List
• Signals Must Allow for Attributes - Additional Overhead
• Variables Take Less Memory Overhead

Constants

• Useful Technique in Making Designs..
  • Readable
  • Re-Usable
  • Maintainable
  • Design Product Life Time Issues
  • Recycling ( Even Designs! ) is Big Business
• Use Constants, Comments, Data Types to Make Your Design Clear!!!

Data Types:

• Scalar
  • integer
  • real
  • enumerated
  • physical
• composite
  • array
  • record
• file
• access

Enumerated Types

• Basic Signal Types are Enumerations
• Some Examples:
  • Bit : ( 0, 1); --Builtin
  • Std_Logic : ( '0', '1', 'Z',.. --Defined in IEEE package
• Useful in Design of Finite State Machines to Express State Values

Physical Types

• Time
  • fS, pS, nS, mS, sec, min, hr
• Current / Voltage
  • na, ua, ma, a
  • mv, v, ..
• Temperature

Composite Type - Arrays

• Indexable Set of Identical Objects
• Enumerations are Arrays
  • Vectored Signals/Ports are Arrays
  • Arrays may be Multi-Dimensional
• ROM Example on Pg 83.. What's it Do?

Unconstrained Arrays

• Powerful Feature
  • Vectored Signal Ranges..
    • Width of Busses
    • Start/Stop Points of Busses
    • Macros can be Defined with 'Growable' Interfaces
    • Specified On Use
  • ..Can be Deferred
  • Example Type Declaration..
    • Type bit_vector is array (natural range <>) of bit;

  Record Type

  • Records Group a Set of Different Type Objects Together
  • Under One Name
  • Example
    • type student is record
      • name : string;
      • Soc Sec Number: string;
      • tuition : real;
      • ..
      • end record;

  Access Types

  • 'Pointers'
  • Build Efficient Dynamic Data Structures
  • eg. Linged Lists
  • Not 'Synthesizable' into CMOS Logic
  • Useful Modeling System Building Blocks
    • FIFO's
    • Stacks

  File Types

  • Syntax Example:
    • TYPE delay_file IS FILE OF Integer;
    • FILE df : delay_file IS IN "/u/jswift/vhdl/delays";
  • Subroutines:
    • procedure READ ( f, d );
    • procedure WRITE ( f, d );
    • function ENDFILE (f); -- returns Boolean

  Sub Types

  • Constrains a Base Type
  • Eases Use of Selected Signal Assignments and Case Statements
    • Remember: You Need to Account for All Possible Values
  • More Expressive: Natural vs Integer
  • Sub Types are Assignment Compatable with Their Base Type
  • Sample Syntax:
    • TYPE Integer IS -2,147,483,647 to +2,147,483,647;
    • SUBTYPE Natural IS Range 0 to +2,147,483,647;

  ---

  How was the class? Send your comments to jswift@vnet.ibm.com
  Return to Class Home Page

  ---

  Copyright 1995, James Swift
  Copying this document without the permission of the author is prohibited and a violation of international copyright laws.