F.1 boris.v

---------------------------------------------------------------
-- B O R I S . V
-- $Id: boris.v,v 1.4 1995/04/25 07:42:18 sharring Exp $
-- Scott Harrington
-- Duke EE Project Spring/Fall 1994
-- Address Tracing System
-- Boris: Buffer Module FPGA
--
-- Each of the four identical Buffer Modules (Boris) handle a
-- 16-bit wide path and consist of this central FPGA, an
-- integrated interface (Natasha) to two 32kx8 bit SRAMs, and
-- several support buffers/drivers/latches.  The Recording
-- Subsystem (Bullwinkle) consists of the Buffer Modules
-- (Boris), control PLDs, and other bus and configuration
-- logic for the FPGAs.
----------------------------------------------------------------

-----------------------
-- I/O descriptions: --
-----------------------

--  Clk: FPGA clock (period > half SRAM access time)
--  Data: 16 bit wide data stream from either local or remote PC
--  Mem: 16 bit wide data path (bidir) to/from SRAM
--  Addr: 15 bit address lines to SRAM
--  SRAM_WE: active low SRAM write enable
--  SRAM_CE: active low SRAM chip enable
--  SRAM_OE: active low SRAM output enable
--  Almost_Full: signals Bullwinkle PLDs to trigger a SRQ (stall request)
--  Full: has equivalent effect of SACK from Rocky; do extract
--  Chip_Select: decoded host address specifies this FPGA (of the 4)
--  Extract: selects extract/record mode of Bullwinkle
--  Trigger: edge triggers read/write to SRAM, then ptr increment
--      Debug: same pad as Init during config, can be read via port 300

ENTITY boris IS
    PORT (
        Clk: IN vlbit;
        Chip_Select: IN vlbit;
        Extract: IN vlbit;
        Trigger: IN vlbit;
        Data: INOUT vlbit_1d(15 downto 0);
        Mem: INOUT vlbit_1d(15 downto 0);
        Addr: OUT vlbit_1d(14 downto 0);
        SRAM_WE: OUT vlbit;
        SRAM_CE: OUT vlbit;
        SRAM_OE: OUT vlbit;
        Empty: BUFFER vlbit;
        Almost_Full: BUFFER vlbit;
        Full: BUFFER vlbit;
        Debug: OUT vlbit
        );
END boris;

ARCHITECTURE behav OF boris IS

-- wp is the RAM address of the next write location
-- The pointers will range from 0 to 32766 in a LFSR sequence
SIGNAL wp: vlbit_1d(14 downto 0);

-- rp is the RAM address of the next read location
SIGNAL rp: vlbit_1d(14 downto 0);

SIGNAL datain: vlbit_1d(15 downto 0);    -- stuff coming in data ports
SIGNAL dataout: vlbit_1d(15 downto 0);   -- stuff going out data ports
SIGNAL memin: vlbit_1d(15 downto 0);     -- stuff coming from mem
SIGNAL memout: vlbit_1d(15 downto 0);    -- stuff going out to mem

-- mem_oe controls the direction of the mem lines (in=0/out=1)
SIGNAL mem_oe: vlbit;
-- data_oe controls the direction of the data lines
SIGNAL data_oe: vlbit;

-- ext, trig, and cs are the CLK-synchronized values of
-- the Extract, Trigger, and Chip_Select inputs
SIGNAL ext: vlbit;
SIGNAL trig: vlbit;
SIGNAL cs: vlbit;

COMPONENT natasha
    PORT(
        Clk: IN vlbit;
        Trig: IN vlbit;
        Ext: IN vlbit;
        CS: IN vlbit;
        WE: OUT vlbit;
        CE: OUT vlbit;
        OE: OUT vlbit
        );
END COMPONENT;

COMPONENT pointers
    PORT(
        Clk: IN vlbit;
        Trig: IN vlbit;
        Ext: IN vlbit;
        CS: IN vlbit;
        Full: BUFFER vlbit;
        Almost_Full: BUFFER vlbit;
        Empty: BUFFER vlbit;
        Addr: BUFFER vlbit_1d(14 downto 0)
        );
END COMPONENT;

BEGIN

    PtrProc : pointers
        PORT MAP(Clk, trig, ext, cs, Full, Almost_Full, Empty, Addr);

    MemProc : natasha
        PORT MAP(Clk, trig, ext, cs, SRAM_WE, SRAM_CE, SRAM_OE);

    SyncInputs : PROCESS
    BEGIN
        WAIT UNTIL Clk'EVENT AND CLK = '1';
    cs <= Chip_Select;
    ext <= Extract;
    trig <= Trigger AND Chip_Select;
    END PROCESS;

    Debug <= Almost_Full;

    -- Set up bidirectional I/O on data and mem lines
    
    data_oe <= cs AND ext;
    mem_oe <= NOT SRAM_WE;       -- SRAM_WE is active low

    BidirDataProc : PROCESS(Clk, data_oe)
    BEGIN
        IF data_oe = '1' THEN
        Data <= dataout;
    ELSIF (Clk'EVENT AND Clk = '1' AND trig)
        datain <= Data;
    END IF;
    END PROCESS;
    
    BidirMemProc : PROCESS(Clk, mem_oe, Mem)
    BEGIN
        IF mem_oe = '1' THEN
        Mem <= memout;
    END IF;
    memin <= Mem;
    END PROCESS;
    
END behav;