Computer Aids for VLSI Design

Steven M. Rubin

Copyright © 1994

Chapter 6: Dynamic Analysis Tools

Section 8 of 8

6.8 Summary

The state of the art demands that designers make compromises in size of design versus level of detail in simulation. The best performing simulators can simulate large designs, but not in sufficient detail to catch subtle errors of the type likely to occur in a process that still involves a great deal of low-level design. Circuit-level simulators can provide all the detail that a designer is likely to need, but cannot process large designs.

A particularly effective approach is to use detailed (circuit-level) simulation to check critical functional or timing paths, and less-detailed simulation for the remainder of the design. The critical sections can be determined using human insight, or through the use of higher-level simulations that identify potential problems in the design.

Although thorough static-analysis techniques proliferate, they still do not replace the actual use of data in debugging a design. Simulation is therefore of continued importance in a CAD system. Simulation tools will have to keep up with the rapidly changing needs of design environments, both in their capabilities and in their style of use.

Questions

1. Invent a more abstract logic block that could replace the cross-coupled NOR gates of the example in the section, Event-Driven Simulation. Give its extended truth table.
2. Show the event queue that results from simulating your logic block under the same assumptions as before (unit gate delay, zero wire delay).
3. Build a truth table for an AND gate that includes the four states: 0, 1, X, and Z (resistive-pullup high).
4. What problems occur when simulating bidirectional MOS transistors? How can these be overcome?
5. How can more accurate models of time improve the quality of simulation that is concerned only with logic values at nodes (and not time)?
6. How can hierarchy aid in simulation?

References

• Abramovici, M.; Levendel, Y.H.; and Menon, P.R., "A Logic Simulation Machine," Proceedings 9th Symposium on Computer Architecture, SIGArch Newsletter, 10:3, 148-157, April 1982.
• Bryant, Randal Everitt, A Switch-Level Simulation Model for Integrated Logic Circuits, PhD dissertation, Massachusetts Institute of Technology Laboratory for Computer Science, report MIT/LCS/TR-259, March 1981.
• Chawla, Basant R.; Gummel, Hermann K.; and Kozak, Paul, "MOTIS-An MOS Timing Simulator," IEEE Transactions on Circuits and Systems, CAS-22:12, 901-910, December 1975.
• Chen, C.F.; Lo, C-Y.; Nham, H.N.; and Subramaniam, Prasad, "The Second Generation MOTIS Mixed-Mode Simulator," Proceedings 21st Design Automation Conference, 10-17, June 1984.
• Denneau, Monty M., "The Yorktown Simulation Engine," Proceedings 19th Design Automation Conference, 55-59, June 1982.
• Frey, Ernest J., "ESIM: A Functional Level Simulation Tool," ICCAD '84, 48-50, November 1984.
• Glasser, Lance A. and Dobberpuhl, Daniel W., The Design and Analysis of VLSI Circuits, Addison-Wesley, Reading, Massachusetts, 1985.
• Grundmann, John W., "Event-Driven MOS Timing Simulator," ICCAD '83, 141-142, September 1983.
• Hennion, B. and Senn, P., "A New Algorithm for Third Generation Circuit Simulators: The One-Step Relaxation Method," Proceedings 22nd Design Automation Conference, 137-143, June 1985.
• IBM, Advanced Statistical Analysis Program (ASTAP), IBM Corporation Data Products Division, Publication SH20-1118-0, White Plains, New York.
• Insinga, Aron K., "Behavioral Modeling in a Structural Logic Simulator," ICCAD '84, 42-44, November 1984.
• Jain, Sunil K. and Agrawal, Vishwani D., "Modeling and Test Generation Algorithms for MOS Circuits," IEEE Transactions on Computers, C-34:5, 426-433, May 1985.
• Lathrop, Richard H. and Kirk, Robert S., "An Extensible Object-Oriented Mixed-Mode Functional Simulation System," Proceedings 22nd Design Automation Conference, 630-636, June 1985.
• Lightner, M.R.; Moceyunas, P.H.; Mueller, H.P.; Vellandi, B.L.; and Vellandi, H.P., "CSIM: The Evolution of a Behavioral Level Simulator from a Functional Simulator: Implementation Issues and Performance Measurements," ICCAD '85, 350-352, November 1985.
• Mead, C. and Conway, L., Introduction to VLSI Systems, Addison-Wesley, Reading, Massachusetts, 1980.
• Miczo, Alexander, Digital Logic Testing and Simulation, Chapter 2: "Combinational Logic Test," Harper and Row, New York, 1986.
• Nagel, L. W., "Spice2: A Computer Program to Simulate Semiconductor Circuits," University of California at Berkeley, ERL-M520, May 1975.
• Newton, Arthur Richard and Sangiovanni-Vincentelli, Alberto L., "Relaxation-Based Electrical Simulation," IEEE Transactions on CAD, CAD-3:4, 308-331, October 1984.
• Roth, J.P., "Diagnosis of Automata Failures: A Calculus and a Method," IBM Journal of Research and Development, 10:4, 278-291, July 1966.
• Saleh, Resve A.; Kleckner, James E.; and Newton, A. Richard, "Iterated Timing Analysis in Splice1," ICCAD '83, 139-140, September 1983.
• Terman, Christopher J. "RSIM-A Logic-level Timing Simulator," Proceedings IEEE International Conference on Computer Design, 437-440, October 1983.
• VLSI Systems Design Staff, "1986 Survey of Logic Simulators," VLSI Systems Design, VII:2, 32-40, February 1986.
• Wang, Paul K.U., "Approaches to Hardware Acceleration of Circuit Simulation," Proceedings IEEE International Conference on Computer Design, 724-726, October 1985.

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