The Hamburg VHDL Archive

The Hamburg
VHDL archive

Welcome to the Hamburg VHDL archive! We intend to provide a collection of free, i.e. public-domain or shareware, VHDL documentation, models, and tools.

This service is provided and maintained by group TECH, Computer Science Dept., University of Hamburg.

Feedback

We are ever looking for additional documents, models, tools and Internet links to improve this server. All contributions, hints, and corrections are welcome. Please contact Norman Hendrich.

Please consider to contribute some of your own models and tools to the VHDL-community in turn for any information downloaded from one of the free VHDL servers.

Internet VHDL Servers and Resources	The following list represents our (subjective) selection of VHDL and EDA/CAD related WWW and ftp-servers. Most public-domain or free VHDL stuff can be found there. For more addresses, try one of the WWW search-engines.
VIUF	The WWW-server of the VHDL International (VI) Users' Forum (VIUF).
FMF	The Free Model Foundation provides free VITAL compliant VHDL models.
comp.lang.vhdl	The only VHDL related Usenet newsgroup. Unfortunately, with sub-average signal-to-noise ratio on some topics.
RASSP	The excellent VHDL server from the RASSP project.
thor.ece.uc.edu	VHDL and CAD/EDA server of the University of California.
cs.utwente.nl	VHDL and CAD/EDA server at the university of Twente.
erm1.u-strasbg.fr	Server of the ERM/PHASE team at the E.N.S.P.S. (University of Strasbourg), with a search engine for their collection of free VHDL models.
vhdluk	VHDL UK server.
www.fp.fmv.se	A server in Sweden.
VHDL, lenguaje...	A Spanish VHDL page.

FAQ

Links to local copies of the comp.lang.vhdl FAQ, which is reposted about monthly. The most recent version can also be obtained from the VHDL International server.

Part 1

general information.

Part 2

VHDL books.

Part 3

products, companies, and services.

Part 4

glossary.

PAL FAQ

The Public Ada Library FAQ.

Documentation

This section presents VHDL documentation of all sort - textbooks, tutorials, tool descriptions, standard proposals, etc.:

VHDL cookbook

The yet classical introduction into VHDL and hardware design by Peter J. Ashenden. It presents the complete description of a non-pipelined 32-bit microprocessor. The book is stored as a 1.5 MByte (Unix .tar.gz) archive with compressed Postscript files for each chapter.

VHDL Kurzanleitung

An introduction to VHDL in German with small design examples and lots of syntax diagrams (what statement is allowed where) by Andreas Mäder. Download either the 162K compressed Postscript file or use the 492K DVI file for online-browsing.

Online tool documentation

Our online-documentation about the Cadence DFW-II, SYNOPSYS VSS, and SYNOPSYS DC tools, in combination with the ES2 or AMS CMOS design kits, by Andreas Mäder (in German).

VHDL, lenguaje para descripcion y modelado de circuitos

A Spanish introduction to circuit design and VHDL with some design examples by Fernando Pardo (260K compressed Postscript). This link is to our local (but possibly old) copy. For the most current version click here.

VHDL: an introduction

An elementary introduction to VHDL, written as his master's thesis by Francis Bruno, in chapters:

cover page (title) (13K Postscript)
table of contents (36K Postscript)
thesis (326K Postscript)
appendix (13K Postscript)

Also by Francis Bruno, a VHDL tutorial: VHDL Representations of some hardware architectures, a basic computer and an assembler:

cover page (title) (13K Postscript)
table of contents (28K Postscript)
report (322K Postscript)
appendix (18K Postscript)
Directory with design files
204K compressed tar (thesis and design files in Unix .tar.gz archive)

VHDL Online

The University of Erlangen (Germany) offers an online VHDL tutorial course in English or German. Given a fast-enough Internet connection, it is also possible to remote-use the examples - design and simulate - using the SpeedCHART and SYNOPSYS tools. Cool!

To use the tools, you have to register (and pay), but the course material and models are free. They also offer a CD-ROM with the complete material.

Introductory VHDL Tutorial (Here)

A VHDL tutorial by Green Mountain Computing Systems. They also sell an educational VHDL compiler for DOS and a professional Windows version. A demo version (Here) is available.

Style guides

A selection of VHDL style and modelling guides:

VHDL modelling guide

The ESA (European Space Agency) guidelines for VHDL modelling. Presents the modelling style required for ESA design qualification with lots of useful tricks and conventions (65K compressed Postscript).

The VHDL Standard

The ESA VHDL status report. An overview of activities, organizations and European tool efforts (127K compressed Postscript).

VHDL modelling guide

US Navy 'Standard Hardware and Reliability Program' (SHARP) Technology Independent Representation of Electronic Products (TIREP) report. Available as 541K compressed Unix .tar.gz archive or in individual chapters:

Chapter 1 (79K compressed Postscript)
Chapter 2 (56K compressed Postscript)
Chapter 3 (80K compressed Postscript)
Chapter 4 (114K compressed Postscript)
Chapter 5 (99K compressed Postscript)
Chapter 6 (61K compressed Postscript)
Chapter 7 (46K compressed Postscript)

VITAL

The current VITAL (VHDL initiative towards ASIC libraries) version 2.2 modelling guidelines and requirements:

VITAL 2.2 cover letter (8K compressed Postscript)
VITAL 2.2 specification (35K compressed Postscript)
VITAL 2.2, appendix A (26K compressed Postscript)
VITAL 2.2, appendix B (32K compressed Postscript)
VITAL 2.2, appendix C (17K compressed Postscript)
VITAL 2.2, appendix D (21K compressed Postscript)
VITAL 2.0 specification (77K compressed Postscript)
VITAL 1.0 requirements (32K compressed Postscript)
VITAL slide presentation (14K compressed Postscript)

Analog VHDL

Analog Extensions to VHDL - Design Objective Document.
IEEE VHDL subPAR 1076.1 report, Version 1.1, 02/03/93 (612K compressed Postscript, 21 pages)

Papers

A collection of several VHDL related technical reports and conference papers.

This section is obviously not really complete. Please submit your papers!

Recursive and repetitive VHDL modelling

Peter J. Ashenden: Recursive and repetitive VHDL modelling. Discusses recursive and iterative structure descriptions for both VHDL-87 and VHDL-93 (117K compressed Postscript).
The corresponding models are available here (53K ASCII).

BABEL machine

W. Hans, J.J. Ruz, F. Sáenz & S. Winkler: A VHDL Specification of a Shared Memory Parallel Machine for Babel (60 pages, 128K compressed Postscript).

Femto-VHDL

John Van Tassel: Femto-VHDL: The semantics of a subset of VHDL and its embedding in the HOL theorem-prover. (479K compressed Postscript tar, or individual chapters) PhD dissertation, University of Cambridge

Verification

Some papers about verification and model checking using VHDL tools:

David P. Appenzeller & Andreas Kuehlmann: Formal Verification of a PowerPC Microprocessor (ICCD-95), 76K compressed Postscript
Jörg Lohse, Jörg Bormann, Michael Payer, and Gerd Venzl: VHDL-Translation for BDD-based Formal Verification (Siemens internal report, 1994), 42K compressed Postscript
Thomas Filkorn, Michael Payer, and Peter Warkentin: Symbolic Verification of Sequential Circuits Synthesized with CALLAS (HLSW-92) 44K compressed Postscript
Jörg Bormann, Jörg Lohse, Michael Payer, and Gerd Venzl: Model Checking in Industrial Hardware Design (DAC-95) 51K compressed Postscript

Models and Packages

Our collection of public-domain VHDL models and packages. If you cannot find a model here, please make sure to check the other VHDL servers listed on top of this page.

std_logic_1164

The standard implementation of the IEEE std_logic_1164 packages from Synopsys, Inc. Please see and respect the copyright notice inside the files.

Numeric_std

The numeric_std arithmetic package for synthesis (Rev. 1.7, Nov. 23 1994, 91K ASCII) based on std_logic_1164.

Mathematical package

The mathematical package VHDL code for real and complex functions. (IEEE VHDL math package study group, proposal 5/28/93, 63K ASCII).

Microprocessors

mc8051
(Here)

Both behavioural and structural (synthesizable!) models of the 8051 µController. The model comes with testbench and several .hex files.

PIC 16C5x

A structural model of the PIC16C5x microcontroller under the GNU public license from Ernesto Romani (romani@ascu.unian.it). The model has been synthesized to a Xilinx 4005 FPGA and comes together with a tool to convert assembler code to a VHDL ROM model.

compressed tar archive (267K, structural VHDL model, assembly packer, some documentation)

Check www.microchip.com for datasheets, documentation, and (free) tools for the PIC series of microcontrollers.

ERC32
(SPARC V7) (Here)

A VHDL simulation model of the ERC32, a radiation tolerant SPARC processor for space applications, complete with documentation and makefiles for the Synopsys and Model Tech simulators.

All models are fully functional with parametrisable timing. The source code and data sheets for the models are provided for free (GNU license) via the ERC32 home page: ERC32 WWW-Server (Here).

The processor consists of integer unit, floating-point unit and memory controller. IU and FPU are compatible with the Cypress 76C01 and 76C02 Sparc V7 processors.

DLX

Both behavioral and RT-level model of Hennessy&Patterson's generic 32bit RISC-processor architecture (without instruction pipeline, however).
compressed tar archive (37K, VHDL description and two simple programs).
directory with the uncompressed files.

SuperScalar DLX (Here)

SuperScalar DLX:
A PPC603-style superscalar mixed behaviour/RTL model of the DLX processor from the TU Darmstadt, Germany:

superscalar, pipelined implementation of DLX (but without floating-point)
4 separate functional untis: branch-resolve, arithmetic-logical, multiply-divide, load-store
5-entry reorder buffer, up to 5 active instructions
4-entry branch-target-buffer
precise exceptions
small 64-entry I-cache and D-cache

The link above contains documentation, all VHDL models, and some test programs in ZIP format. The VHDL code itself is nicely commented and very readable.

GL85

GL85: This circuit is an op-code compatible clone of the i8085 8-bit microprocessor:

gl85 archive(509K compressed tar file) This includes the behavioral and the structural model of the processor, test vectors, and some documentation.
Link to the behavioral VHDL code
Link to the structural VHDL code
Link to the GL85 documentation (including the README file)
Link to the test vector responses

i80386

A simple (and incomplete) behavioral model of the Intel 80386 microprocessor (58K ASCII).

m68000

A simple (and incomplete) behavioral model of the Motorola 68000 microprocessor (36K ASCII).

AMD 2901

AMD 2901 bit slice(Unix .tar.gz)
AMD 2910 bit slice(Unix .tar.gz)

Memory

SRAM, full timing

Our generic SRAM model with full timing, by A. Klindworth. The model uses generic parameters for timing and size, timing checks, startup initialization from file, memory dump to file, etc.

SRAM, no timing

A simple model of a 64Kx8 SRAM without timing, but with startup initialization from a file.

DRAM

A DRAM model by Shannon Hill (posted to comp.lang.vhdl)

EPROM, no timing

A simple 64Kx8 EPROM model without timing checks, but with an Intel-HEX file parser for initialization.

Misc.

CRC LFSR

A cyclic-redundancy-check feedback shift-register, by Russ DeHoedt (posted to comp.lang.vhdl)

MCNC circuits

The standard CAD-benchmark circuits of the MCNC (ftp.mcnc.org).

FPGA course

A collection of circuits and testbenches for our recent FPGA lab. course, which uses Altera FPGAs. For example, you will find another SRAM model and a component to convert ASCII-strings into RS232 (8N1) format. Irdafuse is a circuit to protect an IrDA tranceiver from accidental overload during testing of student's designs.

VHDL-Tools

Our collection of public-domain VHDL tools. If you cannot find a tool here, please make sure to check the other VHDL servers listed on top of this page.

Grammar and Parsers

VHDL-93

VHDL-93 BNF description.

VHDL grammar

VHDL lex/yacc grammar (20K compressed ASCII).

VAUL

VHDL Analyzer and Utility Library (VAUL) parser home page at the University of Dortmund. VAUL is written in C++ and needs flex/bison.
our local but outdated copy (University of Hamburg) (520K tar.gz).

VHDL-93 parser in Prolog

A VHDL-93 compliant parser written in SWI-Prolog with (experimental) VHDL-93 design description browser (gziped tar archive), Readme

VHDL lex/yacc parser

VHDL parser vhdl-lexyacc.1.4 by Thomas Dettmers (19K compressed tar).

VHDL parser in Java

VHDLParser and VHDLTree is a GNU licensed VHDL parser and parse-tree viewer written in Java.

VHDL parser

VHDL parser vhdl-rexlalr.1.2 from the University of Twente, based on the GMD Compiler Tool Box CCTB (35K compressed tar).

Parser frontend vhdlfront.1.1 (100K compressed tar).

VHDL Object Model Parser

A parser written in the REFINE system, Ohio Board of Regents and the University of Cincinnati (36K compressed tar), individual files.

vhdl-2-c

A prototype VHDL-2-C compiler (for sequential statements).

Simulator

ivsim

A free VHDL simulator from Korea! Check the following link for a short README about download, installation, and usage of the tools.

Alliance

The Alliance CAD system (Uiversite de Paris) includes the only free VHDL simulator available. However, only a very small subset of VHDL is supported. The system comes with source code, and can be ftp'd from: (updated links)

primary site
mirror

FreeHDL project

A project to develop a free, open source, GPL'ed VHDL simulator for Linux! The goal of the project is to develop a VHDL-93 compliant simulator with graphical waveform viewer, source level debugger, and with commercial quality.

While some of the parser, simulator and tool code is already available, the project is still looking for new members and supporters!

Editors

Emacs VHDL mode

The official Emacs VHDL mode home page. The mode includes syntax highlighting, indentation, templation insertion, word completion, customized menus, ... everything.

PRISM editor

An editor for Windows 95/98/NT with support for VHDL and several other languages, e.g. ABEL and Synopsys scripts. The editor is shareware; it will disable features after a trial period. The corresponding Windows based help file is free.

Pretty Printing

mvp_v11

(69K compressed tar).

vhdl-nice

The pretty printer of Michael Knieser (version 0.1c).

vhdl2html

A vhdl to HTML converter by Michael Knieser.

Misc

vsplit

A tool to split design files into individual files for each entity, architecture, configuration (12K compressed tar).

vmkr

A makefile generator (version 2.8) to be used in combination with vsplit (110K compressed tar).

blif2vhdl

A BLIF to VHDL converter (51K compressed tar, with SunOS, Solaris, and Linux binaries. Source code (C++) included).

brusey

A FSM-schematic to VHDL code generator, with C sources (the MSC thesis of Thomas C. Mayo) The tool takes xfig drawings of FSMs and generates synthesizable VHDL code:

README(2.5K)
v 2.4 (240K tar)
v 2.0 (65K .tar.Z)
documentation(205K zip)

11.02.99 (FNH) Impressum

http://tech-www.informatik.uni-hamburg.de/vhdl/

FAQ	Links to local copies of the comp.lang.vhdl FAQ, which is reposted about monthly. The most recent version can also be obtained from the VHDL International server.
Part 1	general information.
Part 2	VHDL books.
Part 3	products, companies, and services.
Part 4	glossary.
PAL FAQ	The Public Ada Library FAQ.

Documentation	This section presents VHDL documentation of all sort - textbooks, tutorials, tool descriptions, standard proposals, etc.:
VHDL cookbook	The yet classical introduction into VHDL and hardware design by Peter J. Ashenden. It presents the complete description of a non-pipelined 32-bit microprocessor. The book is stored as a 1.5 MByte (Unix .tar.gz) archive with compressed Postscript files for each chapter.
VHDL Kurzanleitung	An introduction to VHDL in German with small design examples and lots of syntax diagrams (what statement is allowed where) by Andreas Mäder. Download either the 162K compressed Postscript file or use the 492K DVI file for online-browsing.
Online tool documentation	Our online-documentation about the Cadence DFW-II, SYNOPSYS VSS, and SYNOPSYS DC tools, in combination with the ES2 or AMS CMOS design kits, by Andreas Mäder (in German).
VHDL, lenguaje para descripcion y modelado de circuitos	A Spanish introduction to circuit design and VHDL with some design examples by Fernando Pardo (260K compressed Postscript). This link is to our local (but possibly old) copy. For the most current version click here.
VHDL: an introduction	An elementary introduction to VHDL, written as his master's thesis by Francis Bruno, in chapters: cover page (title) (13K Postscript) table of contents (36K Postscript) thesis (326K Postscript) appendix (13K Postscript) Also by Francis Bruno, a VHDL tutorial: VHDL Representations of some hardware architectures, a basic computer and an assembler: cover page (title) (13K Postscript) table of contents (28K Postscript) report (322K Postscript) appendix (18K Postscript) Directory with design files 204K compressed tar (thesis and design files in Unix .tar.gz archive)

VHDL Online	The University of Erlangen (Germany) offers an online VHDL tutorial course in English or German. Given a fast-enough Internet connection, it is also possible to remote-use the examples - design and simulate - using the SpeedCHART and SYNOPSYS tools. Cool! To use the tools, you have to register (and pay), but the course material and models are free. They also offer a CD-ROM with the complete material.
Introductory VHDL Tutorial (Here)	A VHDL tutorial by Green Mountain Computing Systems. They also sell an educational VHDL compiler for DOS and a professional Windows version. A demo version (Here) is available.

Style guides	A selection of VHDL style and modelling guides:
VHDL modelling guide	The ESA (European Space Agency) guidelines for VHDL modelling. Presents the modelling style required for ESA design qualification with lots of useful tricks and conventions (65K compressed Postscript).
The VHDL Standard	The ESA VHDL status report. An overview of activities, organizations and European tool efforts (127K compressed Postscript).
VHDL modelling guide	US Navy 'Standard Hardware and Reliability Program' (SHARP) Technology Independent Representation of Electronic Products (TIREP) report. Available as 541K compressed Unix .tar.gz archive or in individual chapters: Chapter 1 (79K compressed Postscript) Chapter 2 (56K compressed Postscript) Chapter 3 (80K compressed Postscript) Chapter 4 (114K compressed Postscript) Chapter 5 (99K compressed Postscript) Chapter 6 (61K compressed Postscript) Chapter 7 (46K compressed Postscript)

VITAL	The current VITAL (VHDL initiative towards ASIC libraries) version 2.2 modelling guidelines and requirements: VITAL 2.2 cover letter (8K compressed Postscript) VITAL 2.2 specification (35K compressed Postscript) VITAL 2.2, appendix A (26K compressed Postscript) VITAL 2.2, appendix B (32K compressed Postscript) VITAL 2.2, appendix C (17K compressed Postscript) VITAL 2.2, appendix D (21K compressed Postscript) VITAL 2.0 specification (77K compressed Postscript) VITAL 1.0 requirements (32K compressed Postscript) VITAL slide presentation (14K compressed Postscript)

Analog VHDL	Analog Extensions to VHDL - Design Objective Document. IEEE VHDL subPAR 1076.1 report, Version 1.1, 02/03/93 (612K compressed Postscript, 21 pages)

Papers	A collection of several VHDL related technical reports and conference papers. This section is obviously not really complete. Please submit your papers!
Recursive and repetitive VHDL modelling	Peter J. Ashenden: Recursive and repetitive VHDL modelling. Discusses recursive and iterative structure descriptions for both VHDL-87 and VHDL-93 (117K compressed Postscript). The corresponding models are available here (53K ASCII).
BABEL machine	W. Hans, J.J. Ruz, F. Sáenz & S. Winkler: A VHDL Specification of a Shared Memory Parallel Machine for Babel (60 pages, 128K compressed Postscript).
Femto-VHDL	John Van Tassel: Femto-VHDL: The semantics of a subset of VHDL and its embedding in the HOL theorem-prover. (479K compressed Postscript tar, or individual chapters) PhD dissertation, University of Cambridge
Verification	Some papers about verification and model checking using VHDL tools: David P. Appenzeller & Andreas Kuehlmann: Formal Verification of a PowerPC Microprocessor (ICCD-95), 76K compressed Postscript Jörg Lohse, Jörg Bormann, Michael Payer, and Gerd Venzl: VHDL-Translation for BDD-based Formal Verification (Siemens internal report, 1994), 42K compressed Postscript Thomas Filkorn, Michael Payer, and Peter Warkentin: Symbolic Verification of Sequential Circuits Synthesized with CALLAS (HLSW-92) 44K compressed Postscript Jörg Bormann, Jörg Lohse, Michael Payer, and Gerd Venzl: Model Checking in Industrial Hardware Design (DAC-95) 51K compressed Postscript

Models and Packages	Our collection of public-domain VHDL models and packages. If you cannot find a model here, please make sure to check the other VHDL servers listed on top of this page.

std_logic_1164	The standard implementation of the IEEE std_logic_1164 packages from Synopsys, Inc. Please see and respect the copyright notice inside the files.
Numeric_std	The numeric_std arithmetic package for synthesis (Rev. 1.7, Nov. 23 1994, 91K ASCII) based on std_logic_1164.
Mathematical package	The mathematical package VHDL code for real and complex functions. (IEEE VHDL math package study group, proposal 5/28/93, 63K ASCII).

Microprocessors
mc8051 (Here)	Both behavioural and structural (synthesizable!) models of the 8051 µController. The model comes with testbench and several .hex files.
PIC 16C5x	A structural model of the PIC16C5x microcontroller under the GNU public license from Ernesto Romani (romani@ascu.unian.it). The model has been synthesized to a Xilinx 4005 FPGA and comes together with a tool to convert assembler code to a VHDL ROM model. compressed tar archive (267K, structural VHDL model, assembly packer, some documentation) Check www.microchip.com for datasheets, documentation, and (free) tools for the PIC series of microcontrollers.
ERC32 (SPARC V7) (Here)	A VHDL simulation model of the ERC32, a radiation tolerant SPARC processor for space applications, complete with documentation and makefiles for the Synopsys and Model Tech simulators. All models are fully functional with parametrisable timing. The source code and data sheets for the models are provided for free (GNU license) via the ERC32 home page: ERC32 WWW-Server (Here). The processor consists of integer unit, floating-point unit and memory controller. IU and FPU are compatible with the Cypress 76C01 and 76C02 Sparc V7 processors.
DLX	Both behavioral and RT-level model of Hennessy&Patterson's generic 32bit RISC-processor architecture (without instruction pipeline, however). compressed tar archive (37K, VHDL description and two simple programs). directory with the uncompressed files.
SuperScalar DLX (Here)	SuperScalar DLX: A PPC603-style superscalar mixed behaviour/RTL model of the DLX processor from the TU Darmstadt, Germany: superscalar, pipelined implementation of DLX (but without floating-point) 4 separate functional untis: branch-resolve, arithmetic-logical, multiply-divide, load-store 5-entry reorder buffer, up to 5 active instructions 4-entry branch-target-buffer precise exceptions small 64-entry I-cache and D-cache The link above contains documentation, all VHDL models, and some test programs in ZIP format. The VHDL code itself is nicely commented and very readable.
GL85	GL85: This circuit is an op-code compatible clone of the i8085 8-bit microprocessor: gl85 archive(509K compressed tar file) This includes the behavioral and the structural model of the processor, test vectors, and some documentation. Link to the behavioral VHDL code Link to the structural VHDL code Link to the GL85 documentation (including the README file) Link to the test vector responses
i80386	A simple (and incomplete) behavioral model of the Intel 80386 microprocessor (58K ASCII).
m68000	A simple (and incomplete) behavioral model of the Motorola 68000 microprocessor (36K ASCII).
AMD 2901	AMD 2901 bit slice(Unix .tar.gz) AMD 2910 bit slice(Unix .tar.gz)

Memory
SRAM, full timing	Our generic SRAM model with full timing, by A. Klindworth. The model uses generic parameters for timing and size, timing checks, startup initialization from file, memory dump to file, etc.
SRAM, no timing	A simple model of a 64Kx8 SRAM without timing, but with startup initialization from a file.
DRAM	A DRAM model by Shannon Hill (posted to comp.lang.vhdl)
EPROM, no timing	A simple 64Kx8 EPROM model without timing checks, but with an Intel-HEX file parser for initialization.

Misc.
CRC LFSR	A cyclic-redundancy-check feedback shift-register, by Russ DeHoedt (posted to comp.lang.vhdl)
MCNC circuits	The standard CAD-benchmark circuits of the MCNC (ftp.mcnc.org).
FPGA course	A collection of circuits and testbenches for our recent FPGA lab. course, which uses Altera FPGAs. For example, you will find another SRAM model and a component to convert ASCII-strings into RS232 (8N1) format. Irdafuse is a circuit to protect an IrDA tranceiver from accidental overload during testing of student's designs.

VHDL-Tools	Our collection of public-domain VHDL tools. If you cannot find a tool here, please make sure to check the other VHDL servers listed on top of this page.

Grammar and Parsers
VHDL-93	VHDL-93 BNF description.
VHDL grammar	VHDL lex/yacc grammar (20K compressed ASCII).
VAUL	VHDL Analyzer and Utility Library (VAUL) parser home page at the University of Dortmund. VAUL is written in C++ and needs flex/bison. our local but outdated copy (University of Hamburg) (520K tar.gz).
VHDL-93 parser in Prolog	A VHDL-93 compliant parser written in SWI-Prolog with (experimental) VHDL-93 design description browser (gziped tar archive), Readme
VHDL lex/yacc parser	VHDL parser vhdl-lexyacc.1.4 by Thomas Dettmers (19K compressed tar).
VHDL parser in Java	VHDLParser and VHDLTree is a GNU licensed VHDL parser and parse-tree viewer written in Java.
VHDL parser	VHDL parser vhdl-rexlalr.1.2 from the University of Twente, based on the GMD Compiler Tool Box CCTB (35K compressed tar). Parser frontend vhdlfront.1.1 (100K compressed tar).
VHDL Object Model Parser	A parser written in the REFINE system, Ohio Board of Regents and the University of Cincinnati (36K compressed tar), individual files.
vhdl-2-c	A prototype VHDL-2-C compiler (for sequential statements).

Simulator
ivsim	A free VHDL simulator from Korea! Check the following link for a short README about download, installation, and usage of the tools.
Alliance	The Alliance CAD system (Uiversite de Paris) includes the only free VHDL simulator available. However, only a very small subset of VHDL is supported. The system comes with source code, and can be ftp'd from: (updated links) primary site mirror
FreeHDL project	A project to develop a free, open source, GPL'ed VHDL simulator for Linux! The goal of the project is to develop a VHDL-93 compliant simulator with graphical waveform viewer, source level debugger, and with commercial quality. While some of the parser, simulator and tool code is already available, the project is still looking for new members and supporters!

Editors
Emacs VHDL mode	The official Emacs VHDL mode home page. The mode includes syntax highlighting, indentation, templation insertion, word completion, customized menus, ... everything.
PRISM editor	An editor for Windows 95/98/NT with support for VHDL and several other languages, e.g. ABEL and Synopsys scripts. The editor is shareware; it will disable features after a trial period. The corresponding Windows based help file is free.

Pretty Printing
mvp_v11	(69K compressed tar).
vhdl-nice	The pretty printer of Michael Knieser (version 0.1c).
vhdl2html	A vhdl to HTML converter by Michael Knieser.

Misc
vsplit	A tool to split design files into individual files for each entity, architecture, configuration (12K compressed tar).
vmkr	A makefile generator (version 2.8) to be used in combination with vsplit (110K compressed tar).
blif2vhdl	A BLIF to VHDL converter (51K compressed tar, with SunOS, Solaris, and Linux binaries. Source code (C++) included).
brusey	A FSM-schematic to VHDL code generator, with C sources (the MSC thesis of Thomas C. Mayo) The tool takes xfig drawings of FSMs and generates synthesizable VHDL code: README(2.5K) v 2.4 (240K tar) v 2.0 (65K .tar.Z) documentation(205K zip)


11.02.99 (FNH) Impressum	http://tech-www.informatik.uni-hamburg.de/vhdl/