Design Techniques
Implementing Three-State and Bidirectional Buses with Multiplexers in Actel FPGAs
Designing State Machines for FPGAs
Implementing Multipliers with Actel FPGAs
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Design Files
dt1.exe
Synchronous Dividers in Actel FPGAs
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Design Files
dt4.exe
Using FPGAs for Digital PLL Applications
Oscillators for Actel FPGAs
Field Upgradability Using Actel One-Time-Programmable FPGAs
Using the Silicon Explorer for System-level Debug
A Power-on Reset (POR) Circuit for Actel Devices
Three-Stating Actel Device I/O Pins for Board Level Testing
Using Actel Devices in Hot-Socketing Applications
In System Programming ProASIC 500K Devices with Silicon Sculptor
Minimizing Single Event Upset Effects Using Synplicity
RTL Register-Based Memory Implementation
Minimizing Single Event Upset Effects Using Synopsys
Design Techniques for Radiation-Hardened FPGAs
Commercial to Radiation-Hardened Design Migration
Optimal Datapath Generation Using ACTgen
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