-------------------------------------------------------- -- FLASH/SMC interface for MP3 Soc -- Date : 2001.5 -- revision 2.0 -- by Jong seok Park --------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; Entity flash_blk_all is port ( reset, clock : in std_logic; -- for using X1/2 160ns int_data_bus : inout std_logic_vector(7 downto 0); flash_con_reg_we, flash_con_reg_re, flash_con1_reg_we, flash_con1_reg_re, flash_com_addr_reg_we, flash_com_addr_reg_re : in std_logic; SMC_READY_BUSYB : in std_logic; -- CHIP PIN SMC_CEB : out std_logic; -- CHIP PIN SMC_CLE : out std_logic; -- CHIP PIN SMC_ALE : out std_logic; -- CHIP PIN SMC_WEB : out std_logic; -- CHIP PIN SMC_REB : out std_logic; -- CHIP PIN BOARDFLASH_READY_BUSYB : in std_logic; -- CHIP PIN BOARDFLASH_CEB : out std_logic; -- CHIP PIN BOARDFLASH_CLE : out std_logic; -- CHIP PIN BOARDFLASH_ALE : out std_logic; -- CHIP PIN BOARDFLASH_WEB : out std_logic; -- CHIP PIN BOARDFLASH_REB : out std_logic; -- CHIP PIN FLASH_DATA_IO : inout std_logic_vector(7 downto 0); -- CHIP PIN FLASH2DMA_DATA : out std_logic_vector(7 downto 0); DMA2FLASH_DATA : in std_logic_vector(7 downto 0); DMA_ADDRESS : out std_logic_vector(9 downto 0); DMA_WE : out std_logic; DMA_RE : out std_logic ); End flash_blk_all; ---------------------------------------------------------- Architecture flash_blk_all_a of flash_blk_all is component flash_con_reg port ( reset,clock : in std_logic; re,we : in std_logic; int_data_bus : inout std_logic_vector(7 downto 0); READY_BUSYB : in std_logic; CEB,CLE,ALE : out std_logic; WEB,REB : out std_logic; M0,M1,M2,M3 : out std_logic ); end component; component flash_con1_reg port ( reset,clock : in std_logic; re,we : in std_logic; int_data_bus : inout std_logic_vector(7 downto 0); done528 : in std_logic; done528clear : out std_logic; flash_select : out std_logic ); end component; component flash_com_addr_reg port ( reset,clock : in std_logic; re,we,we1 : in std_logic; int_data_bus : inout std_logic_vector(7 downto 0); command_address : out std_logic_vector(7 downto 0); flash_data : in std_logic_vector(7 downto 0) ); end component; ---------------------------------------------------------------------- signal reg_web_sig : std_logic; signal reg_reb_sig : std_logic; signal mode0,mode1,mode2,mode3 : std_logic; signal command_address : std_logic_vector(7 downto 0); signal flash_com_addr_data : std_logic_vector(7 downto 0); signal DMA_ADDR : std_logic_vector(9 downto 0); signal DMA_READ_ADDR : std_logic_vector(9 downto 0); signal DMA_WRITE_ADDR : std_logic_vector(9 downto 0); signal DMA_WE_sig : std_logic; signal DMA_RE_sig : std_logic; signal programming_we,seq_reading_re : std_logic; signal FLASH_REB_sig : std_logic; signal FLASH_WEB_sig : std_logic; signal DMA_ADDR_CLOCK: std_logic; signal done528_1,done528_2,done528 : std_logic; signal done528clear : std_logic; -- for SMC/on board FLASH select signal FLASH_CEB,FLASH_CLE,FLASH_ALE, FLASH_WEB, FLASH_REB : std_logic; signal FLASH_READY_BUSYB : std_logic; signal flash_select : std_logic; Begin u1: flash_con_reg port map ( reset => reset, clock => clock, re => flash_con_reg_re, we => flash_con_reg_we, int_data_bus => int_data_bus, READY_BUSYB => FLASH_READY_BUSYB, CEB => FLASH_CEB, CLE => FLASH_CLE, ALE => FLASH_ALE, WEB => reg_web_sig, REB => reg_reb_sig, M0 => mode0, M1 => mode1, M2 => mode2, M3 => mode3 ); -------------------------------------------------------------- -- M0 : address/command latch DATA write -- M1 : address/command latch DATA read -- M2 : sequential write(programming) 528 byte DATA write -- M3 : sequential read 528 byte DATA read -------------------------------------------------------------- u2 : flash_con1_reg port map ( reset => reset, clock => clock, re => flash_con1_reg_re, we => flash_con1_reg_we, int_data_bus => int_data_bus, done528 => done528, done528clear => done528clear, flash_select => flash_select ); u3: flash_com_addr_reg port map ( reset => reset, clock => clock, re => flash_com_addr_reg_re, we => flash_com_addr_reg_we, we1 => flash_reb_sig, int_data_bus => int_data_bus, command_address => command_address, flash_data => flash_com_addr_data ); FLASH_DATA_IO <= command_address when (mode0='1' and mode1='0' and mode2='0' and mode3='0') else -- write DMA2FLASH_DATA when (mode0='0' and mode1='0' and mode2='1' and mode3='0') else -- write "ZZZZZZZZ"; process(FLASH_DATA_IO,mode0,mode1,mode2,mode3) begin if (mode0='0' and mode1='1' and mode2='0' and mode3='0') then flash_com_addr_data <= FLASH_DATA_IO; else flash_com_addr_data <= "00000000"; end if; end process; process(FLASH_DATA_IO,mode0,mode1,mode2,mode3) begin if (mode0='0' and mode1='0' and mode2='0' and mode3='1') then FLASH2DMA_DATA <= FLASH_DATA_IO; else FLASH2DMA_DATA <= "00000000"; end if; end process; -------------------------------------------------------------- -- M0 : address/command latch DATA write -- M1 : address/command latch DATA read -- M2 : sequential write(programming) 528 byte DATA write -- M3 : sequential read 528 byte DATA read -------------------------------------------------------------- process(reset,clock,mode0,mode1,mode2,mode3,reg_web_sig,reg_reb_sig,programming_we,seq_reading_re) begin if reset='1' then FLASH_WEB_sig <= '1'; FLASH_REB_sig <= '1'; elsif clock='0' and clock'event then if mode0='1' and mode1='0' and mode2='0' and mode3='0' then FLASH_WEB_sig <= reg_web_sig; FLASH_REB_sig <= '1'; elsif mode0='0' and mode1='1' and mode2='0' and mode3='0' then FLASH_WEB_sig <= '1'; FLASH_REB_sig <= reg_reb_sig; elsif mode0='0' and mode1='0' and mode2='1' and mode3='0' then FLASH_WEB_sig <= programming_we; FLASH_REB_sig <= '1'; elsif mode0='0' and mode1='0' and mode2='0' and mode3='1' then FLASH_WEB_sig <= '1'; FLASH_REB_sig <= seq_reading_re; end if; end if; end process; FLASH_WEB <= FLASH_WEB_sig; FLASH_REB <= FLASH_REB_sig; -------------------------------------------------------------------------- process(reset,clock,mode0,mode1,mode2,mode3,seq_reading_re,DMA_ADDR) begin if reset='1' then seq_reading_re <='1'; elsif clock='1' and clock'event then if mode0='0' and mode1='0' and mode2='0' and mode3='1' then if DMA_ADDR = "1000010000" then -- 528 seq_reading_re <= '1'; else seq_reading_re <= not seq_reading_re; end if; else seq_reading_re <= '1'; end if; end if; end process; process(reset,clock,seq_reading_re) begin if reset='1' then DMA_WE_sig <= '0'; elsif clock='0' and clock'event then DMA_WE_sig <= not seq_reading_re; end if; end process; ----------------------------------------------------------------------- process(FLASH_REB_sig,FLASH_WEB_sig,mode0,mode1,mode2,mode3) begin if mode0='0' and mode1='0' and mode2='0' and mode3='1' then DMA_ADDR_CLOCK <= FLASH_REB_sig; elsif mode0='0' and mode1='0' and mode2='1' and mode3='0' then DMA_ADDR_CLOCK <= FLASH_WEB_sig; elsif mode0='0' and mode1='1' and mode2='0' and mode3='0' then DMA_ADDR_CLOCK <= '0'; elsif mode0='1' and mode1='0' and mode2='0' and mode3='0' then DMA_ADDR_CLOCK <= '0'; else DMA_ADDR_CLOCK <= '0'; end if; end process; --DMA_ADDR_CLOCK <= FLASH_REB_sig; -------------------------------------------------------------------------------- process(reset,mode0,mode1,mode2,mode3,DMA_READ_ADDR,DMA_ADDR_CLOCK,done528clear) begin if reset='1' or done528clear='1' then DMA_READ_ADDR <= "0000000000"; -- flash write, dma read elsif DMA_ADDR_CLOCK='0' and DMA_ADDR_CLOCK'event then if DMA_READ_ADDR = "1000010000" then DMA_READ_ADDR <= DMA_READ_ADDR; else DMA_READ_ADDR <= DMA_READ_ADDR + "0000000001"; end if; end if; end process; -------------------------------------------------------------------------------- process(reset,clock,mode0,mode1,mode2,mode3,DMA_WRITE_ADDR,DMA_ADDR_CLOCK,done528clear) begin if reset='1' or done528clear='1' then DMA_WRITE_ADDR <= "1111111111"; -- flash read, dma write elsif DMA_ADDR_CLOCK='0' and DMA_ADDR_CLOCK'event then if DMA_WRITE_ADDR = "1000010000" then DMA_WRITE_ADDR <= DMA_WRITE_ADDR; else DMA_WRITE_ADDR <= DMA_WRITE_ADDR + "0000000001"; end if; end if; end process; -------------------------------------------------------------------------------- process(mode0,mode1,mode2,mode3,DMA_READ_ADDR,DMA_WRITE_ADDR) begin if (mode0='0' and mode1='0' and mode2='0' and mode3='1') then DMA_ADDR <= DMA_WRITE_ADDR; elsif (mode0='0' and mode1='0' and mode2='1' and mode3='0') then DMA_ADDR <= DMA_READ_ADDR; else DMA_ADDR <= "0000000000"; end if; end process; ------------------------------------------------------------------------ process(reset,clock,mode0,mode1,mode2,mode3,programming_we,DMA_ADDR) begin if reset='1' then programming_we <= '1'; elsif clock='0' and clock'event then if mode0='0' and mode1='0' and mode2='1' and mode3='0' then if DMA_ADDR = "1000010000" then programming_we <= '1'; else programming_we <= not programming_we; end if; else programming_we <= '1'; end if; end if; end process; --process(reset,clock,programming_we) --begin -- if reset='1' then -- DMA_RE_sig <= '0'; -- elsif clock='0' and clock'event then DMA_RE_sig <= not programming_we; -- end if; --end process; process(reset,DMA_WE_sig,DMA_ADDR,done528clear) begin if reset='1' or done528clear='1' then done528_1 <= '0'; elsif DMA_WE_sig='1' and DMA_WE_sig'event then if DMA_ADDR="1000001111" then done528_1 <='1'; else done528_1 <='0'; end if; end if; end process; --------------------------------------------------- process(reset,DMA_RE_sig,DMA_ADDR,done528clear) begin if reset='1' or done528clear='1' then done528_2 <= '0'; elsif DMA_RE_sig='0' and DMA_RE_sig'event then if DMA_ADDR="1000001111" then done528_2 <='1'; else done528_2 <='0'; end if; end if; end process; ------------------------------------------------- done528 <= done528_1 or done528_2; DMA_WE <= DMA_WE_sig; DMA_RE <= DMA_RE_sig; DMA_ADDRESS <= DMA_ADDR; --------------------------------------------- -- for SMC/on board FLASH select process(flash_select,FLASH_CEB,FLASH_CLE,FLASH_ALE, FLASH_WEB, FLASH_REB, BOARDFLASH_READY_BUSYB,SMC_READY_BUSYB) begin if flash_select='0' then -- on board FLASH SMC_CEB <= '1'; SMC_CLE <= '0'; SMC_ALE <= '0'; SMC_WEB <='1'; SMC_REB <='1'; BOARDFLASH_CEB <= FLASH_CEB; BOARDFLASH_CLE <= FLASH_CLE; BOARDFLASH_ALE <= FLASH_ALE; BOARDFLASH_WEB <=FLASH_WEB; BOARDFLASH_REB <= FLASH_REB; FLASH_READY_BUSYB <= BOARDFLASH_READY_BUSYB; else -- SMC SMC_CEB <= FLASH_CEB; SMC_CLE <= FLASH_CLE; SMC_ALE <= FLASH_ALE; SMC_WEB <= FLASH_WEB; SMC_REB <= FLASH_REB; BOARDFLASH_CEB <= '1'; BOARDFLASH_CLE <= '0'; BOARDFLASH_ALE <= '0'; BOARDFLASH_WEB <= '1'; BOARDFLASH_REB <= '1'; FLASH_READY_BUSYB <= SMC_READY_BUSYB; end if; end process; End flash_blk_all_a; --------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; ---------------------------------------------------------------------- Entity flash_con_reg is port ( reset,clock : in std_logic; re,we : in std_logic; int_data_bus : inout std_logic_vector(7 downto 0); READY_BUSYB : in std_logic; CEB,CLE,ALE : out std_logic; WEB,REB : out std_logic; M0,M1,M2,M3 : out std_logic ); end flash_con_reg; ---------------------------------------------------------------------- Architecture flash_con_reg_a of flash_con_reg is signal flash_con_reg_sig : std_logic_vector(7 downto 0); begin Process(reset,clock,we,int_data_bus,flash_con_reg_sig) begin if reset='1' then flash_con_reg_sig(6 downto 0) <= "1000011"; elsif clock='0' and clock'event then if we='1' then flash_con_reg_sig(6 downto 0) <= int_data_bus(6 downto 0); else flash_con_reg_sig(6 downto 0) <= flash_con_reg_sig(6 downto 0); end if; end if; end process; flash_con_reg_sig(7) <= READY_BUSYB; int_data_bus <= flash_con_reg_sig when re='1' else "ZZZZZZZZ"; CEB <= flash_con_reg_sig(6); CLE <= flash_con_reg_sig(5); ALE <= flash_con_reg_sig(4); WEB <= flash_con_reg_sig(1); REB <= flash_con_reg_sig(0); M0 <= not flash_con_reg_sig(3) and not flash_con_reg_sig(2); M1 <= not flash_con_reg_sig(3) and flash_con_reg_sig(2); M2 <= flash_con_reg_sig(3) and not flash_con_reg_sig(2); M3 <= flash_con_reg_sig(3) and flash_con_reg_sig(2); -------------------------------------------------------------- -- M0 : address/command latch DATA write -- M1 : address/command latch DATA read -- M2 : sequential write(programming) 528 byte DATA write -- M3 : sequential read 528 byte DATA read -------------------------------------------------------------- end flash_con_reg_a; ---------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; ---------------------------------------------------------------------- Entity flash_con1_reg is port ( reset,clock : in std_logic; re,we : in std_logic; int_data_bus : inout std_logic_vector(7 downto 0); done528 : in std_logic; done528clear : out std_logic; flash_select : out std_logic ); end flash_con1_reg; Architecture flash_con1_reg_a of flash_con1_reg is signal flash_con1_reg_sig : std_logic_vector(7 downto 0); begin Process(reset,clock,we,int_data_bus,flash_con1_reg_sig) begin if reset='1' then flash_con1_reg_sig(6 downto 0) <= "0000000"; elsif clock='0' and clock'event then if we='1' then flash_con1_reg_sig(6 downto 0) <= int_data_bus(6 downto 0); else flash_con1_reg_sig(6 downto 0) <= flash_con1_reg_sig(6 downto 0); end if; end if; end process; flash_con1_reg_sig(7) <= done528; done528clear <= flash_con1_reg_sig(6); -- for SMC/on board FLASH select flash_select <= flash_con1_reg_sig(0); int_data_bus <= flash_con1_reg_sig when re='1' else "ZZZZZZZZ"; End flash_con1_reg_a; ---------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; ---------------------------------------------------------------------- Entity flash_com_addr_reg is port ( reset,clock : in std_logic; re,we,we1 : in std_logic; int_data_bus : inout std_logic_vector(7 downto 0); command_address : out std_logic_vector(7 downto 0); flash_data : in std_logic_vector(7 downto 0) ); end flash_com_addr_reg; ---------------------------------------------------------------------- Architecture flash_com_addr_reg_a of flash_com_addr_reg is signal flash_com_addr_reg_sig : std_logic_vector(7 downto 0); begin Process(reset,clock,we,int_data_bus,flash_com_addr_reg_sig,flash_data) begin if reset='1' then flash_com_addr_reg_sig <= "00000000"; elsif clock='0' and clock'event then if we='1' then flash_com_addr_reg_sig <= int_data_bus; elsif we1='0' then flash_com_addr_reg_sig <= flash_data; else flash_com_addr_reg_sig <= flash_com_addr_reg_sig; end if; end if; end process; int_data_bus <= flash_com_addr_reg_sig when re='1' else "ZZZZZZZZ"; command_address <= flash_com_addr_reg_sig; end flash_com_addr_reg_a; ----------------------------------------------------------------------