-------------------------------------------------------- -- MMC interface for MP3 Soc -- Date : 2001.5 -- revision 2.0 -- by Jong seok Park --------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; Entity mmc_con_blk is port ( x1, reset, clock : in std_logic; -- for using X1/2 160ns int_data_bus : inout std_logic_vector(7 downto 0); mmc_cmd_reg_we, mmc_cmd_reg_re, mmc_data_reg_we, mmc_data_reg_re, mmc_con_reg_we, mmc_con_reg_re : in std_logic; MMC_CLK : out std_logic; -- CHIP PIN MMC_CMD_SPI_OUT : out std_logic; -- CHIP PIN MMC_DATA_SPI_IN : in std_logic; -- CHIP PIN MMC_VCCEN : out std_logic; -- CHIP PIN MMC_RS_CSB : out std_logic; -- CHIP PIN MMC2DMA_DATA : out std_logic_vector(7 downto 0); -- DMA2MMC_DATA : in std_logic_vector(7 downto 0); DMA_ADDRESS : out std_logic_vector(9 downto 0); DMA_WE : out std_logic -- DMA_RE : out std_logic ); End mmc_con_blk; ---------------------------------------------------------- Architecture mmc_con_blk_a of mmc_con_blk is component mmc_cmd_reg port ( reset,clock : in std_logic; re,we : in std_logic; int_data_bus : inout std_logic_vector(7 downto 0); mmc_cmd : out std_logic_vector(7 downto 0) ); end component; component mmc_data_reg port ( reset,clock : in std_logic; re,we : in std_logic; int_data_bus : inout std_logic_vector(7 downto 0); SPI_DATAIN_WE : in std_logic; mmc_data : in std_logic_vector(7 downto 0) ); end component; component mmc_con_reg port ( reset,clock : in std_logic; re,we : in std_logic; int_data_bus : inout std_logic_vector(7 downto 0); MMC_VCCEN : out std_logic; MMC_RS_CSB : out std_logic; -- CHIP PIN dma_block_read_start : out std_logic; dma_block_read_end : in std_logic; cmd_tx_start : out std_logic; cmd_tx_start_off : in std_logic; cmd_tx_done : in std_logic ); end component; component mmc_clk_gen port ( x1,reset,clock : in std_logic; mmc_cmd : in std_logic_vector(7 downto 0); mmc_data : out std_logic_vector(7 downto 0); MMC_CMD_SPI_OUT : out std_logic; -- CHIP PIN MMC_DATA_SPI_IN : in std_logic; -- CHIP PIN cmd_tx_start : in std_logic; cmd_tx_start_off : out std_logic; cmd_tx_done : out std_logic; dma_block_read_start : in std_logic; dma_block_read_end : out std_logic; MMC2DMA_data : out std_logic_vector(7 downto 0); DMA_ADDR : out std_logic_vector(9 downto 0); DMA_WE : out std_logic; MMC_CLK : out std_logic ); end component; ---------------------------------------------------------------------- signal mmc_cmd : std_logic_vector(7 downto 0); signal mmc_data : std_logic_vector(7 downto 0); signal cmd_tx_start, cmd_tx_done : std_logic; signal cmd_tx_start_off : std_logic; signal dma_read_block_start : std_logic; signal dma_read_block_end : std_logic; Begin u1 : mmc_cmd_reg port map ( reset => reset, clock => clock, re => mmc_cmd_reg_re, we => mmc_cmd_reg_we, int_data_bus => int_data_bus, mmc_cmd => mmc_cmd ); u2 : mmc_data_reg port map ( reset => reset, clock => clock, re => mmc_data_reg_re, we => mmc_data_reg_we, int_data_bus => int_data_bus, SPI_DATAIN_WE => cmd_tx_start_off, mmc_data => mmc_data ); u3: mmc_con_reg port map ( reset => reset, clock => clock, re => mmc_con_reg_re, we => mmc_con_reg_we, int_data_bus => int_data_bus, MMC_VCCEN => MMC_VCCEN, MMC_RS_CSB => MMC_RS_CSB, dma_block_read_start => dma_read_block_start, dma_block_read_end => dma_read_block_end, cmd_tx_start => cmd_tx_start, cmd_tx_start_off => cmd_tx_start_off, cmd_tx_done => cmd_tx_done ); u4 : mmc_clk_gen port map ( x1 => x1, reset => reset, clock => clock, mmc_cmd => mmc_cmd, mmc_data => mmc_data, MMC_CMD_SPI_OUT => MMC_CMD_SPI_OUT, MMC_DATA_SPI_IN => MMC_DATA_SPI_IN, cmd_tx_start => cmd_tx_start, cmd_tx_start_off => cmd_tx_start_off, cmd_tx_done => cmd_tx_done, dma_block_read_start => dma_read_block_start, dma_block_read_end => dma_read_block_end, MMC2DMA_data => MMC2DMA_DATA, DMA_ADDR => DMA_ADDRESS, DMA_WE => DMA_WE, MMC_CLK => MMC_CLK ); ---------------------------------------------------------------------- end mmc_con_blk_a; ---------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; ---------------------------------------------------------------------- Entity mmc_cmd_reg is port ( reset,clock : in std_logic; re,we : in std_logic; int_data_bus : inout std_logic_vector(7 downto 0); mmc_cmd : out std_logic_vector(7 downto 0) ); end mmc_cmd_reg; ---------------------------------------------------------------------- Architecture mmc_cmd_reg_a of mmc_cmd_reg is signal mmc_cmd_reg_sig : std_logic_vector(7 downto 0); begin Process(reset,clock,we,int_data_bus,mmc_cmd_reg_sig) begin if reset='1' then mmc_cmd_reg_sig <= "00000000"; elsif clock='0' and clock'event then if we='1' then mmc_cmd_reg_sig <= int_data_bus; else mmc_cmd_reg_sig <= mmc_cmd_reg_sig; end if; end if; end process; int_data_bus <= mmc_cmd_reg_sig when re='1' else "ZZZZZZZZ"; mmc_cmd <= mmc_cmd_reg_sig; end mmc_cmd_reg_a; ---------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; ---------------------------------------------------------------------- Entity mmc_data_reg is port ( reset,clock : in std_logic; re,we : in std_logic; int_data_bus : inout std_logic_vector(7 downto 0); SPI_DATAIN_WE : in std_logic; mmc_data : in std_logic_vector(7 downto 0) ); end mmc_data_reg; Architecture mmc_data_reg_a of mmc_data_reg is signal mmc_data_reg_sig : std_logic_vector(7 downto 0); -- not ready signal mmc_data_sig : std_logic_vector(7 downto 0); begin Process(reset,clock,we,int_data_bus,mmc_data_reg_sig,mmc_data,SPI_DATAIN_WE) begin if reset='1' then mmc_data_reg_sig <= "00000000"; elsif clock='0' and clock'event then if we='1' then mmc_data_reg_sig <= int_data_bus; elsif SPI_DATAIN_WE='1' then mmc_data_reg_sig <= mmc_data; else mmc_data_reg_sig <= mmc_data_reg_sig; end if; end if; end process; int_data_bus <= mmc_data_reg_sig when re='1' else "ZZZZZZZZ"; -- not ready mmc_data_sig <= mmc_data; End mmc_data_reg_a; ---------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; ---------------------------------------------------------------------- Entity mmc_con_reg is port ( reset,clock : in std_logic; re,we : in std_logic; int_data_bus : inout std_logic_vector(7 downto 0); MMC_VCCEN : out std_logic; MMC_RS_CSB : out std_logic; -- CHIP PIN dma_block_read_start : out std_logic; dma_block_read_end : in std_logic; cmd_tx_start : out std_logic; cmd_tx_start_off : in std_logic; cmd_tx_done : in std_logic ); end mmc_con_reg; ---------------------------------------------------------------------- Architecture mmc_con_reg_a of mmc_con_reg is signal mmc_con_reg_sig : std_logic_vector(7 downto 0); begin Process(reset,clock,we,int_data_bus,mmc_con_reg_sig) begin if reset='1' then mmc_con_reg_sig(7 downto 4) <= "0000"; elsif clock='0' and clock'event then if we='1' then mmc_con_reg_sig(7 downto 4) <= int_data_bus(7 downto 4); else mmc_con_reg_sig(7 downto 4) <= mmc_con_reg_sig(7 downto 4); end if; end if; end process; --------------------------- -- CMD_TXD_START --------------------------- process(reset,clock,we,cmd_tx_start_off,int_data_bus) begin if reset='1' then mmc_con_reg_sig(1) <= '0'; elsif clock='0' and clock'event then if we='1' then mmc_con_reg_sig(1) <= int_data_bus(1); elsif cmd_tx_start_off='1' then mmc_con_reg_sig(1) <= '0'; else mmc_con_reg_sig(1) <= mmc_con_reg_sig(1); end if; end if; end process; --------------------------- -- CMD_TXD_DONE --------------------------- process(reset,clock,cmd_tx_done) begin if reset='1' then mmc_con_reg_sig(0) <= '0'; elsif clock='0' and clock'event then mmc_con_reg_sig(0) <= cmd_tx_done; end if; end process; --------------------------- -- BLOCK_READ_START --------------------------- process(reset,clock,we,int_data_bus,dma_block_read_end) begin if reset='1' then mmc_con_reg_sig(2) <= '0'; elsif clock='0' and clock'event then if we='1' then mmc_con_reg_sig(2) <= int_data_bus(2); elsif dma_block_read_end='1' then mmc_con_reg_sig(2) <= '0'; else mmc_con_reg_sig(2) <= mmc_con_reg_sig(2); end if; end if; end process; --------------------------- -- BLOCK_READ_END --------------------------- process(reset,clock,we,int_data_bus,dma_block_read_end) begin if reset='1' then mmc_con_reg_sig(3) <= '0'; elsif clock='0' and clock'event then if dma_block_read_end='1' then mmc_con_reg_sig(3) <= '1'; elsif we='1' then mmc_con_reg_sig(3) <= int_data_bus(3); else mmc_con_reg_sig(3) <= mmc_con_reg_sig(3); end if; end if; end process; int_data_bus <= mmc_con_reg_sig when re='1' else "ZZZZZZZZ"; MMC_VCCEN <= mmc_con_reg_sig(7); MMC_RS_CSB <= mmc_con_reg_sig(4); cmd_tx_start <= mmc_con_reg_sig(1); dma_block_read_start <= mmc_con_reg_sig(2); end mmc_con_reg_a; ---------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; ---------------------------------------------------------------------- Entity mmc_clk_gen is port ( x1,reset,clock : in std_logic; mmc_cmd : in std_logic_vector(7 downto 0); mmc_data : out std_logic_vector(7 downto 0); MMC_CMD_SPI_OUT : out std_logic; -- CHIP PIN MMC_DATA_SPI_IN : in std_logic; -- CHIP PIN cmd_tx_start : in std_logic; cmd_tx_start_off : out std_logic; cmd_tx_done : out std_logic; dma_block_read_start : in std_logic; dma_block_read_end : out std_logic; MMC2DMA_data : out std_logic_vector(7 downto 0); DMA_ADDR : out std_logic_vector(9 downto 0); DMA_WE : out std_logic; MMC_CLK : out std_logic ); end mmc_clk_gen; Architecture mmc_clk_gen_a of mmc_clk_gen is component mmc_getdata_reg port ( reset,clock : in std_logic; en : in std_logic; getdata : in std_logic; outdata : out std_logic ); end component; signal mmc_clk_current_state : std_logic_vector(3 downto 0); signal mmc_clk_current_state_delay : std_logic_vector(3 downto 0); signal mmc_clk_next_state : std_logic_vector(3 downto 0); signal cmd_tx_start_off_d : std_logic; signal cmd_tx_done_sig : std_logic; signal mmc_clk_en : std_logic; signal MMC_CLK_sig : std_logic; signal mmc_data_sig : std_logic_vector(7 downto 0); signal MMC_CMD_SPI_OUT_sig : std_logic; -----------------DMA signal dma_mmc_clk_current_state, dma_mmc_clk_next_state : std_logic_vector(3 downto 0); signal mmc_getdata_register_en : std_logic_vector(7 downto 0); signal MMC2DMA_data_sig : std_logic_vector(7 downto 0); signal MMC4DMA_clk : std_logic; signal MMC4DMA_clk_en : std_logic; signal mmc2dma_1byte_end : std_logic; signal DMA_ADDR_sig : std_logic_vector(9 downto 0); signal DMA_WE_sig : std_logic; signal dma_block_read_end_sig : std_logic; signal dma_block_read_start_delay : std_logic; begin process(reset,clock,dma_block_read_start) begin if reset='1' then dma_block_read_start_delay <= '0'; elsif clock='1' and clock'event then dma_block_read_start_delay <= dma_block_read_start; end if; end process; process(reset,clock,cmd_tx_start,mmc_clk_current_state,mmc_clk_next_state) begin if reset='1' then mmc_clk_current_state <= "0000"; elsif clock='1' and clock'event then if cmd_tx_start='1' then mmc_clk_current_state <= mmc_clk_next_state; else mmc_clk_current_state <= mmc_clk_current_state; end if; end if; end process; process(mmc_clk_current_state) begin case mmc_clk_current_state is when "0000" => mmc_clk_next_state <= "0001"; when "0001" => mmc_clk_next_state <= "0010"; when "0010" => mmc_clk_next_state <= "0011"; when "0011" => mmc_clk_next_state <= "0100"; when "0100" => mmc_clk_next_state <= "0101"; when "0101" => mmc_clk_next_state <= "0110"; when "0110" => mmc_clk_next_state <= "0111"; when "0111" => mmc_clk_next_state <= "1000"; when "1000" => mmc_clk_next_state <= "0000"; when others => mmc_clk_next_state <= "0000"; end case; end process; ----------------------------------------------------- process(mmc_clk_current_state) begin if mmc_clk_current_state="1000" then cmd_tx_start_off_d <='1'; else cmd_tx_start_off_d <='0'; end if; end process; process(reset,clock,cmd_tx_start_off_d) begin if reset='1' then cmd_tx_start_off <='0'; elsif clock='1' and clock'event then cmd_tx_start_off <= cmd_tx_start_off_d; end if; end process; --------------------------------------------- process(reset,clock,mmc_clk_current_state,cmd_tx_start_off_d,cmd_tx_done_sig) begin if reset='1' then cmd_tx_done_sig <='0'; elsif clock='0' and clock'event then if mmc_clk_current_state="1000" then cmd_tx_done_sig <= cmd_tx_start_off_d; elsif mmc_clk_current_state = "0000" then cmd_tx_done_sig <= cmd_tx_done_sig; else cmd_tx_done_sig <= '0'; end if; end if; end process; cmd_tx_done <= cmd_tx_done_sig; --------------------------------------------- -- MMC_CLK generation --------------------------------------------- process(x1,reset,mmc_clk_current_state) begin if reset='1' then mmc_clk_en <= '0'; elsif x1='1' and x1'event then if (mmc_clk_current_state(0) or mmc_clk_current_state(1) or mmc_clk_current_state(2) or mmc_clk_current_state(3)) = '1' then mmc_clk_en <='1'; else mmc_clk_en <='0'; end if; end if; end process; MMC_CLK_sig <= (not (cmd_tx_start and clock)) and mmc_clk_en; MMC_CLK <= MMC_CLK_sig or MMC4DMA_clk; -- for DMA access process(reset,clock,mmc_clk_current_state) begin if reset='1' then mmc_clk_current_state_delay <="0000"; elsif clock='0' and clock'event then mmc_clk_current_state_delay <= mmc_clk_current_state; end if; end process; process(reset,clock,mmc_cmd,mmc_clk_current_state_delay) begin if reset='1' then MMC_CMD_SPI_OUT_sig <= '0'; elsif clock='1' and clock'event then case mmc_clk_current_state_delay is when "0000" => MMC_CMD_SPI_OUT_sig <= mmc_cmd(7); when "0001" => MMC_CMD_SPI_OUT_sig <= mmc_cmd(6); when "0010" => MMC_CMD_SPI_OUT_sig <= mmc_cmd(5); when "0011" => MMC_CMD_SPI_OUT_sig <= mmc_cmd(4); when "0100" => MMC_CMD_SPI_OUT_sig <= mmc_cmd(3); when "0101" => MMC_CMD_SPI_OUT_sig <= mmc_cmd(2); when "0110" => MMC_CMD_SPI_OUT_sig <= mmc_cmd(1); when "0111" => MMC_CMD_SPI_OUT_sig <= mmc_cmd(0); when "1000" => MMC_CMD_SPI_OUT_sig <= '0'; when others => MMC_CMD_SPI_OUT_sig <= '0'; end case; end if; end process; process(MMC_CMD_SPI_OUT_sig,dma_block_read_start) begin if dma_block_read_start='1' then MMC_CMD_SPI_OUT <= '1'; else MMC_CMD_SPI_OUT <= MMC_CMD_SPI_OUT_sig; end if; end process; process(reset,MMC_CLK_sig,mmc_clk_current_state,MMC_DATA_SPI_IN,mmc_data_sig) begin if reset='1' then mmc_data_sig <= "00000000"; elsif MMC_CLK_sig='1' and MMC_CLK_sig'event then if mmc_clk_current_state="0001" then mmc_data_sig(7) <= MMC_DATA_SPI_IN; mmc_data_sig(6 downto 0) <= mmc_data_sig(6 downto 0); elsif mmc_clk_current_state="0010" then mmc_data_sig(6) <= MMC_DATA_SPI_IN; mmc_data_sig(5 downto 0) <= mmc_data_sig(5 downto 0); mmc_data_sig(7) <= mmc_data_sig(7); elsif mmc_clk_current_state="0011" then mmc_data_sig(5) <= MMC_DATA_SPI_IN; mmc_data_sig(7 downto 6) <= mmc_data_sig(7 downto 6); mmc_data_sig(4 downto 0) <= mmc_data_sig(4 downto 0); elsif mmc_clk_current_state="0100" then mmc_data_sig(4) <= MMC_DATA_SPI_IN; mmc_data_sig(7 downto 5) <= mmc_data_sig(7 downto 5); mmc_data_sig(3 downto 0) <= mmc_data_sig(3 downto 0); elsif mmc_clk_current_state="0101" then mmc_data_sig(3) <= MMC_DATA_SPI_IN; mmc_data_sig(7 downto 4) <= mmc_data_sig(7 downto 4); mmc_data_sig(2 downto 0) <= mmc_data_sig(2 downto 0); elsif mmc_clk_current_state="0110" then mmc_data_sig(2) <= MMC_DATA_SPI_IN; mmc_data_sig(7 downto 3) <= mmc_data_sig(7 downto 3); mmc_data_sig(1 downto 0) <= mmc_data_sig(1 downto 0); elsif mmc_clk_current_state="0111" then mmc_data_sig(1) <= MMC_DATA_SPI_IN; mmc_data_sig(0) <= mmc_data_sig(0); mmc_data_sig(7 downto 2) <= mmc_data_sig(7 downto 2); elsif mmc_clk_current_state="1000" then mmc_data_sig(0) <= MMC_DATA_SPI_IN; mmc_data_sig(7 downto 1) <= mmc_data_sig(7 downto 1); else mmc_data_sig <= mmc_data_sig; end if; end if; end process; mmc_data <= mmc_data_sig; ---------------------------------------------------------------------- -- DMA processing ---------------------------------------------------------------------- process(reset,clock,dma_mmc_clk_current_state,dma_mmc_clk_next_state,dma_block_read_start_delay) begin if reset='1' then dma_mmc_clk_current_state <= "0000"; elsif clock='1' and clock'event then if dma_block_read_start='1' then dma_mmc_clk_current_state <= dma_mmc_clk_next_state; else dma_mmc_clk_current_state <= dma_mmc_clk_current_state; end if; end if; end process; process(dma_mmc_clk_current_state) begin case dma_mmc_clk_current_state is when "0000" => dma_mmc_clk_next_state <= "0001"; when "0001" => dma_mmc_clk_next_state <= "0010"; when "0010" => dma_mmc_clk_next_state <= "0011"; when "0011" => dma_mmc_clk_next_state <= "0100"; when "0100" => dma_mmc_clk_next_state <= "0101"; when "0101" => dma_mmc_clk_next_state <= "0110"; when "0110" => dma_mmc_clk_next_state <= "0111"; when "0111" => dma_mmc_clk_next_state <= "1000"; when "1000" => dma_mmc_clk_next_state <= "1001"; when "1001" => dma_mmc_clk_next_state <= "1010"; when "1010" => dma_mmc_clk_next_state <= "0001"; when others => dma_mmc_clk_next_state <= "0000"; end case; end process; --------------------------- -- getting data register --------------------------- process(reset,x1,dma_mmc_clk_current_state,dma_block_read_start) begin if reset='1' then mmc_getdata_register_en <= "00000000"; elsif x1='1' and x1'event then if dma_block_read_start='1' then if dma_mmc_clk_current_state ="0000" or dma_mmc_clk_current_state="1010" then mmc_getdata_register_en <= "00000001"; elsif dma_mmc_clk_current_state ="0001" then mmc_getdata_register_en <= "00000010"; elsif dma_mmc_clk_current_state ="0010" then mmc_getdata_register_en <= "00000100"; elsif dma_mmc_clk_current_state ="0011" then mmc_getdata_register_en <= "00001000"; elsif dma_mmc_clk_current_state ="0100" then mmc_getdata_register_en <= "00010000"; elsif dma_mmc_clk_current_state ="0101" then mmc_getdata_register_en <= "00100000"; elsif dma_mmc_clk_current_state ="0110" then mmc_getdata_register_en <= "01000000"; elsif dma_mmc_clk_current_state ="0111" then mmc_getdata_register_en <= "10000000"; else mmc_getdata_register_en <= "00000000"; end if; else mmc_getdata_register_en <= "00000000"; end if; end if; end process; process(x1,clock,reset,dma_block_read_start, dma_mmc_clk_current_state,MMC4DMA_clk_en) begin if reset='1' then MMC4DMA_clk_en <= '0' ; elsif x1='1' and x1'event then if dma_block_read_start='1' then if clock='0' and (dma_mmc_clk_current_state="0000" or dma_mmc_clk_current_state="1010") then MMC4DMA_clk_en <= '1'; elsif clock='0' and dma_mmc_clk_current_state="1000" then MMC4DMA_clk_en <= '0'; else MMC4DMA_clk_en <= MMC4DMA_clk_en; end if; else MMC4DMA_clk_en <= '0'; end if; end if; end process; MMC4DMA_clk <= MMC4DMA_clk_en and clock; u1: mmc_getdata_reg port map(reset,MMC4DMA_clk,mmc_getdata_register_en(0),MMC_DATA_SPI_IN,MMC2DMA_data_sig(7)); u2: mmc_getdata_reg port map(reset,MMC4DMA_clk,mmc_getdata_register_en(1),MMC_DATA_SPI_IN,MMC2DMA_data_sig(6)); u3: mmc_getdata_reg port map(reset,MMC4DMA_clk,mmc_getdata_register_en(2),MMC_DATA_SPI_IN,MMC2DMA_data_sig(5)); u4: mmc_getdata_reg port map(reset,MMC4DMA_clk,mmc_getdata_register_en(3),MMC_DATA_SPI_IN,MMC2DMA_data_sig(4)); u5: mmc_getdata_reg port map(reset,MMC4DMA_clk,mmc_getdata_register_en(4),MMC_DATA_SPI_IN,MMC2DMA_data_sig(3)); u6: mmc_getdata_reg port map(reset,MMC4DMA_clk,mmc_getdata_register_en(5),MMC_DATA_SPI_IN,MMC2DMA_data_sig(2)); u7: mmc_getdata_reg port map(reset,MMC4DMA_clk,mmc_getdata_register_en(6),MMC_DATA_SPI_IN,MMC2DMA_data_sig(1)); u8: mmc_getdata_reg port map(reset,MMC4DMA_clk,mmc_getdata_register_en(7),MMC_DATA_SPI_IN,MMC2DMA_data_sig(0)); process(reset,clock,dma_mmc_clk_current_state,MMC2DMA_data_sig) begin if reset='1' then MMC2DMA_data <= "00000000"; elsif clock='0' and clock'event then if dma_mmc_clk_current_state="1000" then MMC2DMA_data <= MMC2DMA_data_sig; end if; end if; end process; ------------------------------------------------------------- process(reset,clock,dma_mmc_clk_current_state) begin if reset='1' then mmc2dma_1byte_end <= '0'; elsif clock='0' and clock'event then if dma_mmc_clk_current_state="1000" then mmc2dma_1byte_end <= '1' ; else mmc2dma_1byte_end <= '0' ; end if; end if; end process; DMA_WE_sig <= mmc2dma_1byte_end; DMA_WE <= DMA_WE_sig; ------------------------------------------------------------- process(reset,clock,dma_mmc_clk_current_state,DMA_ADDR_sig,dma_block_read_start_delay) begin if reset='1' then DMA_ADDR_sig <= "0000000000"; elsif clock='0' and clock'event then if dma_block_read_start_delay='1' then if dma_mmc_clk_current_state="1010" then DMA_ADDR_sig <= DMA_ADDR_sig + "0000000001"; else DMA_ADDR_sig <= DMA_ADDR_sig; end if; else DMA_ADDR_sig <= "0000000000"; end if; end if; end process; DMA_ADDR <= DMA_ADDR_sig; ------------------------------------------------------------- process(reset,clock,dma_mmc_clk_current_state,DMA_ADDR_sig) begin if reset='1' then dma_block_read_end_sig <='0'; elsif clock='0' and clock'event then if DMA_ADDR_sig = "1000000001" and dma_mmc_clk_current_state="1001" then dma_block_read_end_sig <='1'; else dma_block_read_end_sig <='0'; end if; end if; end process; dma_block_read_end <= dma_block_read_end_sig; End mmc_clk_gen_a; -------------------------------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; ---------------------------------------------------------------------- Entity mmc_getdata_reg is port ( reset,clock : in std_logic; en : in std_logic; getdata : in std_logic; outdata : out std_logic ); end mmc_getdata_reg; Architecture mmc_getdata_reg_a of mmc_getdata_reg is signal out_sig : std_logic; begin process(reset,clock,en,getdata,out_sig) begin if reset='1' then out_sig <= '0'; elsif clock='1' and clock'event then if en='1' then out_sig <= getdata; else out_sig <= out_sig; end if; end if; end process; outdata <= out_sig; end mmc_getdata_reg_a; -----------------------------------------------------------------