-------------------------------------------------------- -- MP3 decoder interface for MP3 Soc -- Date : 2001.5 -- revision 2.0 -- by Jong seok Park --------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; Entity mp3_blk is port ( reset, clock : in std_logic; -- for using X1/2 int_data_bus : inout std_logic_vector(7 downto 0); mp3cntr_reg_we, mp3cntr_reg_re, mp3data_reg_we, mp3data_reg_re : in std_logic; MP3_REQ : in std_logic; -- for external Mp3 decoder MP3_SDO : out std_logic; -- for external Mp3 decoder MP3_CLK : out std_logic; -- for external Mp3 decoder -- for TEST -- MP3_CNTR_REG : out std_logic_vector(7 downto 0); -- MP3_512_END : out std_logic; -- MP3_CLKEN_REG : out std_logic; -- MP3_CLKEN_REQ : out std_logic; -- MP3DATACOUNT : out std_logic_vector(3 downto 0); --- for DMA interface DMA_MP3DATA_IN : in std_logic_vector(7 downto 0); DMA_MP3_ADDR : out std_logic_vector(9 downto 0); DMA_MP3_RE : out std_logic ); End mp3_blk; ---------------------------------------------------------- Architecture mp3_blk_a of mp3_blk is ---------------------------------- Component mp3cntr_reg port ( reset,clock : in std_logic; we,re : in std_logic; int_data_bus : inout std_logic_vector(7 downto 0); mp3SDO_end_flag : in std_logic; mp3clken : out std_logic; mp3SDO_dir_sel : out std_logic; mp3req : in std_logic; mp3reg_end : in std_logic -- for TEST -- MP3_CNTR_REG : out std_logic_vector(7 downto 0) ); end component; ---------------------------------- Component mp3data_reg port ( reset,clock : in std_logic; we,re : in std_logic; int_data_bus : inout std_logic_vector(7 downto 0); mp3data_reg_out : out std_logic_vector(7 downto 0); mp3clk_state : in std_logic_vector(3 downto 0); mp3data_count_state : in std_logic_vector(3 downto 0); mp3SDO_end_flag : in std_logic; mp3buffer_readen : in std_logic; mp3reg_end_flag : in std_logic; mp3reg_read_addr : out std_logic_vector(9 downto 0); mp3buffer_output : out std_logic_vector(7 downto 0); ----------for DMA interface DMA_mp3buffer_out : in std_logic_vector(7 downto 0); DMA_mp3buffer_addr : out std_logic_vector(9 downto 0); DMA_MP3_RE : out std_logic ); end component; ---------------------------------- component mp3clk_gen port ( reset,clock : in std_logic; mp3clken : in std_logic; mp3data_count : in std_logic_vector(3 downto 0); mp3clk : out std_logic; -- for external Mp3 decoder mp3dataclk : out std_logic; -- for internal SOD latching... mp3clk_state : out std_logic_vector(3 downto 0) ); end component; ---------------------------------- component mp3_serial_out port ( reset,clock : in std_logic; mp3clk,mp3dataclk : in std_logic; SDO_dir : in std_logic; --'1' : MSB first , '0' : LSB first mp3clk_state : in std_logic_vector(3 downto 0); mp3data_reg : in std_logic_vector(7 downto 0); MP3_SDO : out std_logic; MP3_SDO_end_flag : out std_logic; mp3reg_read_addr : in std_logic_vector(9 downto 0); mp3data_count_state : out std_logic_vector(3 downto 0); mp3reg_read_end : out std_logic ); end component; ---------------------------------- signal mp3clken_reg,mp3clken_req, mp3clken_sig : std_logic; signal mp3SDO_dir_sel : std_logic; signal mp3data_reg_out : std_logic_vector(7 downto 0); signal mp3clk_sig, mp3dataclk_sig : std_logic; signal mp3SDO_end_flag : std_logic; signal mp3clk_state : std_logic_vector(3 downto 0); signal mp3data_count_state : std_logic_vector(3 downto 0); signal mp3reg_read_end : std_logic; signal mp3buffer_data : std_logic_vector(7 downto 0); signal mp3reg_read_addr : std_logic_vector(9 downto 0); Begin U1 : mp3cntr_reg port map ( reset => reset, clock => clock, we => mp3cntr_reg_we, re => mp3cntr_reg_re, int_data_bus => int_data_bus, mp3SDO_end_flag => mp3SDO_end_flag, mp3clken => mp3clken_reg, mp3SDO_dir_sel => mp3SDO_dir_sel, mp3req => MP3_REQ, mp3reg_end => mp3reg_read_end -- for TEST -- MP3_CNTR_REG => MP3_CNTR_REG ); U2 : mp3data_reg port map ( reset => reset, clock => clock, we => mp3data_reg_we, re => mp3data_reg_re, int_data_bus => int_data_bus, mp3data_reg_out => mp3data_reg_out, mp3clk_state => mp3clk_state, mp3data_count_state => mp3data_count_state, mp3SDO_end_flag => mp3SDO_end_flag, mp3buffer_readen => mp3clken_reg, mp3reg_read_addr => mp3reg_read_addr, mp3reg_end_flag => mp3reg_read_end, mp3buffer_output => mp3buffer_data, DMA_mp3buffer_out => DMA_MP3DATA_IN, DMA_mp3buffer_addr => DMA_MP3_ADDR, DMA_MP3_RE => DMA_MP3_RE ); U3 : mp3clk_gen port map ( reset => reset, clock => clock, mp3clken => mp3clken_sig, mp3data_count => mp3data_count_state, mp3clk => mp3clk_sig, mp3dataclk => mp3dataclk_sig, mp3clk_state => mp3clk_state ); U4 : mp3_serial_out port map ( reset => reset, clock => clock, mp3clk => mp3clk_sig, mp3dataclk => mp3dataclk_sig, SDO_dir => mp3SDO_dir_sel, mp3clk_state => mp3clk_state, mp3data_reg => mp3buffer_data,--mp3data_reg_out, MP3_SDO => MP3_SDO, MP3_SDO_end_flag => mp3SDO_end_flag, mp3reg_read_addr => mp3reg_read_addr, mp3data_count_state => mp3data_count_state, mp3reg_read_end => mp3reg_read_end ); --------------------------------------------------- process(reset,clock,MP3_REQ,mp3data_count_state) begin if reset='1' then mp3clken_req <='1'; elsif clock='0' and clock'event then -- if mp3data_count_state="1101" and MP3_REQ='0' then -- mp3clken_req <= '0'; -- elsif mp3data_count_state="1101" and MP3_REQ='1' then -- mp3clken_req <= '1'; -- -- elsif mp3data_count_state="0001" and MP3_REQ='0' then -- mp3clken_req <= '0'; -- elsif mp3data_count_state="0001" and MP3_REQ='1' then -- mp3clken_req <= '1'; -- -- else -- mp3clken_req <= mp3clken_req; -- end if; if MP3_REQ='0' then if mp3data_count_state = "1101" then mp3clken_req <= '0'; else mp3clken_req <= mp3clken_req; end if; elsif MP3_REQ='1' then mp3clken_req <= '1'; end if; end if; end process; ------------------------------------------------- mp3clken_sig <= mp3clken_reg and mp3clken_req; MP3_CLK <= mp3clk_sig; -- for TEST --MP3_512_END <= mp3reg_read_end; --MP3_CLKEN_REG <= mp3clken_reg; --MP3_CLKEN_REQ <= mp3clken_req; --MP3DATACOUNT <= mp3data_count_state; End mp3_blk_a; ---------------------------------------------------------------------- -- MP3 8bit DATA register -- SFR area located : ??h ---------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; --library lpm; --use lpm.LPM_COMPONENTS.all; --USE work.LPM_COMPONENTS.all; Entity mp3data_reg IS port ( reset,clock : in std_logic; we,re : in std_logic; int_data_bus : inout std_logic_vector(7 downto 0); mp3data_reg_out : out std_logic_vector(7 downto 0); mp3clk_state : in std_logic_vector(3 downto 0); mp3data_count_state : in std_logic_vector(3 downto 0); mp3SDO_end_flag : in std_logic; mp3buffer_readen : in std_logic; mp3reg_end_flag : in std_logic; mp3reg_read_addr : out std_logic_vector(9 downto 0); mp3buffer_output : out std_logic_vector(7 downto 0); ----------for DMA interface DMA_mp3buffer_out: in std_logic_vector(7 downto 0); DMA_mp3buffer_addr: out std_logic_vector(9 downto 0); DMA_MP3_RE : out std_logic ); End mp3data_reg; Architecture mp3data_reg_a of mp3data_reg is signal mp3data_reg_sig : std_logic_vector(7 downto 0); --signal mp3buffer_out : std_logic_vector(7 downto 0); signal mp3buffer_data : std_logic_vector(7 downto 0); signal mp3buffer_we : std_logic; signal mp3buffer_re : std_logic; signal mp3buffer_re_delay : std_logic; signal mp3buffer_addr : std_logic_vector(9 downto 0); signal mp3reg_write_addr_sig : std_logic_vector(9 downto 0); signal mp3reg_read_addr_sig : std_logic_vector(9 downto 0); Begin process(reset,clock,we,int_data_bus,mp3data_reg_sig) begin if reset = '1' then mp3data_reg_sig <= "00000000"; elsif clock='0' and clock'event then if we = '1' then mp3data_reg_sig <= int_data_bus; else mp3data_reg_sig <= mp3data_reg_sig; end if; end if; end process; int_data_bus <= mp3data_reg_sig when re='1' else "ZZZZZZZZ"; mp3data_reg_out <= mp3data_reg_sig; process(reset,clock,we,mp3reg_write_addr_sig,mp3reg_end_flag) begin if reset ='1' or mp3reg_end_flag='1' then mp3reg_write_addr_sig <="0000000000"; elsif clock='1' and clock'event then if we='1' then mp3reg_write_addr_sig <= mp3reg_write_addr_sig + "0000000001"; else mp3reg_write_addr_sig <= mp3reg_write_addr_sig; end if; end if; end process; process(reset,clock,mp3SDO_end_flag,mp3reg_read_addr_sig,mp3reg_end_flag) begin if reset ='1' or mp3reg_end_flag='1' then mp3reg_read_addr_sig <="0000000000"; elsif clock='0' and clock'event then if mp3SDO_end_flag='1' then mp3reg_read_addr_sig <= mp3reg_read_addr_sig + "0000000001"; else mp3reg_read_addr_sig <= mp3reg_read_addr_sig; end if; end if; end process; mp3reg_read_addr <=mp3reg_read_addr_sig; ------------------------------------------------ -- MODELING INT_RAM with LPM_RAM_DQ ------------------------------------------------- process(we,clock,reset) begin if reset='1' then mp3buffer_we <= '0'; elsif clock='0' and clock'event then mp3buffer_we <= we; end if; end process; --u1: lpm_ram_dq -- GENERIC MAP( -- LPM_WIDTH => 8, -- LPM_WIDTHAD => 9, -- LPM_INDATA => "UNREGISTERED", -- --LPM_ADDRESS_CONTROL => "UNREGISTERED", -- this option NOT VAILD... -- LPM_ADDRESS_CONTROL => "REGISTERED", -- LPM_OUTDATA => "REGISTERED" -- ) -- -- PORT MAP( -- data => mp3data_reg_sig, -- address => mp3buffer_addr, -- we => mp3buffer_we, -- q => mp3buffer_out, -- before TRI -- --inclock => VCC_H, -- inclock => clock, -- jspark 2001_08_31 -- outclock => clock -- ); DMA_mp3buffer_addr <= mp3buffer_addr; DMA_MP3_RE <= mp3buffer_re; ------------------------------------------------------------------ process(reset,clock,mp3buffer_readen,mp3reg_write_addr_sig,mp3reg_read_addr_sig) begin if reset='1' then mp3buffer_addr <= "0000000000"; elsif clock='1' and clock'event then if mp3buffer_readen='1' then mp3buffer_addr <= mp3reg_read_addr_sig; else mp3buffer_addr <= mp3reg_write_addr_sig; end if; end if; end process; ------------------------------------------------------------------ process(reset,clock,mp3clk_state,mp3data_count_state,mp3buffer_readen) begin if reset='1' then mp3buffer_re <= '0'; elsif clock='1' and clock'event then if ((mp3clk_state="0000" and mp3data_count_state="0000") or --(mp3clk_state="1000" and mp3data_count_state="1001")) and (mp3clk_state="1000" and mp3data_count_state="1101")) and mp3buffer_readen='1' then mp3buffer_re <= '1'; else mp3buffer_re <= '0'; end if; end if; end process; ----------------------------------- process(reset,clock,mp3buffer_re) begin if reset='1' then mp3buffer_re_delay<='0'; elsif clock='0' and clock'event then mp3buffer_re_delay <= mp3buffer_re; end if; end process; ----------------------------------- process(reset,clock,mp3SDO_end_flag,DMA_mp3buffer_out, mp3buffer_data,mp3buffer_re_delay) begin if reset='1' then mp3buffer_data <= "00000000"; elsif clock='0' and clock'event then if mp3buffer_re_delay='1' then mp3buffer_data <= DMA_mp3buffer_out; else mp3buffer_data <= mp3buffer_data; end if; end if; end process; mp3buffer_output <= mp3buffer_data; ------------------------------------------------------------------ End mp3data_reg_a; --------------------------------------------------------------------- ---------------------------------------------------------------------- -- MP3 8bit CONTROL register -- SFR area located : ??h ------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; Entity mp3cntr_reg IS port ( reset,clock : in std_logic; we,re : in std_logic; int_data_bus : inout std_logic_vector(7 downto 0); mp3SDO_end_flag : in std_logic; mp3clken : out std_logic; mp3SDO_dir_sel : out std_logic; mp3req : in std_logic; mp3reg_end : in std_logic -- for TEST -- MP3_CNTR_REG : out std_logic_vector(7 downto 0) ); End mp3cntr_reg; Architecture mp3cntr_reg_a of mp3cntr_reg is Component mp3cntr_reg_sel port ( reset,clock : in std_logic; we : in std_logic; control_in : in std_logic; off_in : in std_logic; reg_in : in std_logic; reg_out : out std_logic ); End component; signal mp3cntr_reg_sig : std_logic_vector(7 downto 0); signal GND_L : std_logic; signal not_mp3reg_end, not_mp3SDO_end_flag,not_mp3req : std_logic; begin GND_L <= '0'; not_mp3reg_end <= not mp3reg_end; not_mp3SDO_end_flag <= not mp3SDO_end_flag; not_mp3req <= not mp3req; U1 : mp3cntr_reg_sel port map (reset,clock,we,mp3cntr_reg_sig(0),mp3reg_end, int_data_bus(0),mp3cntr_reg_sig(0)); U2 : mp3cntr_reg_sel port map (reset,clock,we,mp3cntr_reg_sig(1),GND_L, int_data_bus(1),mp3cntr_reg_sig(1)); U3 : mp3cntr_reg_sel port map (reset,clock,we,mp3reg_end,GND_L, int_data_bus(2),mp3cntr_reg_sig(2)); U4 : mp3cntr_reg_sel port map (reset,clock,we,mp3SDO_end_flag,not_mp3SDO_end_flag, int_data_bus(3),mp3cntr_reg_sig(3)); U5 : mp3cntr_reg_sel port map (reset,clock,we,mp3req,not_mp3req, int_data_bus(4),mp3cntr_reg_sig(4)); U6 : mp3cntr_reg_sel port map (reset,clock,we,mp3cntr_reg_sig(5),GND_L, int_data_bus(5),mp3cntr_reg_sig(5)); U7 : mp3cntr_reg_sel port map (reset,clock,we,mp3cntr_reg_sig(6),GND_L, int_data_bus(6),mp3cntr_reg_sig(6)); U8 : mp3cntr_reg_sel port map (reset,clock,we,mp3cntr_reg_sig(7),GND_L, int_data_bus(7),mp3cntr_reg_sig(7)); int_data_bus <= mp3cntr_reg_sig when re='1' else "ZZZZZZZZ"; mp3clken <= mp3cntr_reg_sig(0);-- (input) mp3SDO_dir_sel <= mp3cntr_reg_sig(1);-- (input) --mp3reg_end mp3cntr_reg_sig(2) all 512 byte trasfer done.. (output) --mp3SDO_end_flag mp3cntr_reg_sig(3) => mp3SDO_end_flag (output) 1byte transfer done~! --MP3_REQ mp3cntr_reg_sig(4) => MP3_REQ (output) -- for TEST --MP3_CNTR_REG <= mp3cntr_reg_sig; End mp3cntr_reg_a; ------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; Entity mp3cntr_reg_sel is port ( reset,clock : in std_logic; we : in std_logic; control_in : in std_logic; off_in : in std_logic; reg_in : in std_logic; reg_out : out std_logic ); End mp3cntr_reg_sel; Architecture mp3cntr_reg_sel_a of mp3cntr_reg_sel is signal reg_out_sig : std_logic; begin process(clock,reset,we,off_in,reg_in,control_in,reg_out_sig) begin if reset='1' then reg_out_sig <= '0'; elsif clock='0' and clock'event then if we='1' then reg_out_sig <= reg_in; elsif off_in='1' then reg_out_sig <= '0'; elsif control_in='1' then reg_out_sig <= '1'; else reg_out_sig <= reg_out_sig; end if; end if; end process; reg_out <= reg_out_sig; End mp3cntr_reg_sel_a; ------------------------------------------------------------------------- -- MP3 CLOCK and DATA latching clock generator ------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; Entity mp3clk_gen IS port ( reset,clock : in std_logic; mp3clken : in std_logic; mp3data_count : in std_logic_vector(3 downto 0); mp3clk : out std_logic; -- for extenal Mp3 decoder mp3dataclk : out std_logic; -- for internal SOD latching... mp3clk_state : out std_logic_vector(3 downto 0) ); End mp3clk_gen; Architecture mp3clk_gen_a of mp3clk_gen is signal mp3clk_current_state : std_logic_vector(3 downto 0); signal mp3clk_next_state : std_logic_vector(3 downto 0); signal mp3clk_sig : std_logic; signal mp3data_outen_clk : std_logic; Begin process(reset,clock,mp3clk_next_state,mp3clken) begin if reset='1' then mp3clk_current_state <= "0000"; elsif clock='0' and clock'event then if mp3clken='1' then mp3clk_current_state <= mp3clk_next_state; else --mp3clk_current_state <= "0000"; mp3clk_current_state <= mp3clk_current_state; end if; end if; end process; ----------------------------------------------- process(mp3clk_current_state) begin case mp3clk_current_state is when "0000" => mp3clk_next_state <= "0001"; when "0001" => mp3clk_next_state <= "0010"; when "0010" => mp3clk_next_state <= "0011"; when "0011" => mp3clk_next_state <= "0100"; when "0100" => mp3clk_next_state <= "0101"; when "0101" => mp3clk_next_state <= "0110"; when "0110" => mp3clk_next_state <= "0111"; when "0111" => mp3clk_next_state <= "1000"; when "1000" => mp3clk_next_state <= "0000"; when others => mp3clk_next_state <= "0000"; end case; end process; ----------------------------------------------- process(mp3clk_current_state,reset,clock,mp3clk_sig,mp3data_count) begin if reset='1' then mp3clk_sig <= '0'; elsif clock='1' and clock'event then if mp3data_count = "1001" or mp3data_count = "1010" or mp3data_count="1011" or mp3data_count = "1100" or mp3data_count = "1101" then mp3clk_sig <= '0'; else if mp3clk_current_state="0100" then mp3clk_sig <= '1'; elsif mp3clk_current_state="1000" then mp3clk_sig <= '0'; else mp3clk_sig <= mp3clk_sig; end if; end if; end if; end process; ------------------------------------------------- process(mp3clk_current_state,reset,clock,mp3data_outen_clk) begin if reset='1' then mp3data_outen_clk <= '0'; elsif clock='1' and clock'event then if mp3clk_current_state="0010" then mp3data_outen_clk <= '1'; elsif mp3clk_current_state="0110" then mp3data_outen_clk <= '0'; else mp3data_outen_clk <= mp3data_outen_clk; end if; end if; end process; mp3clk <= mp3clk_sig; mp3dataclk <= mp3data_outen_clk; mp3clk_state <= mp3clk_current_state; End mp3clk_gen_a; ------------------------------------------------------------------------- ------------------------------------------------------------------------- -- MP3 Serial DATA output control ------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; Entity mp3_serial_out IS port ( reset,clock : in std_logic; mp3clk,mp3dataclk : in std_logic; SDO_dir : in std_logic; --'1' : MSB first , '0' : LSB first mp3clk_state : in std_logic_vector(3 downto 0); mp3data_reg : in std_logic_vector(7 downto 0); MP3_SDO : out std_logic; MP3_SDO_end_flag : out std_logic; mp3reg_read_addr : in std_logic_vector(9 downto 0); mp3data_count_state : out std_logic_vector(3 downto 0); mp3reg_read_end : out std_logic ); End mp3_serial_out; Architecture mp3_serial_out_a of mp3_serial_out is signal mp3data_count_current_state : std_logic_vector(3 downto 0); signal mp3data_count_next_state : std_logic_vector(3 downto 0); signal mp3_sdo_end : std_logic; signal mp3reg_end_flag0 : std_logic; signal mp3reg_end_flag1 : std_logic; signal mp3reg_end_flag : std_logic; begin ---------------------------------------------- -- MP3 DATA shift 1bit output ---------------------------------------------- process(mp3dataclk,reset,mp3data_count_next_state) begin if reset='1' then mp3data_count_current_state <= "0000"; elsif mp3dataclk='1' and mp3dataclk'event then mp3data_count_current_state <= mp3data_count_next_state; end if; end process; process(mp3data_count_current_state) begin case mp3data_count_current_state is when "0000" => mp3data_count_next_state <= "0001"; when "0001" => mp3data_count_next_state <= "0010"; when "0010" => mp3data_count_next_state <= "0011"; when "0011" => mp3data_count_next_state <= "0100"; when "0100" => mp3data_count_next_state <= "0101"; when "0101" => mp3data_count_next_state <= "0110"; when "0110" => mp3data_count_next_state <= "0111"; when "0111" => mp3data_count_next_state <= "1000"; when "1000" => mp3data_count_next_state <= "1001"; when "1001" => mp3data_count_next_state <= "1010"; when "1010" => mp3data_count_next_state <= "1011"; when "1011" => mp3data_count_next_state <= "1100"; when "1100" => mp3data_count_next_state <= "1101"; when "1101" => mp3data_count_next_state <= "0001"; when others => mp3data_count_next_state <= "0000"; end case; end process; -------------------------------------------------- process(reset,mp3dataclk,mp3data_reg,mp3data_count_current_state,SDO_dir) begin if reset='1' then MP3_SDO <= '0'; elsif mp3dataclk='1' and mp3dataclk'event then if SDO_dir='1' then --if mp3data_count_current_state="0000" or mp3data_count_current_state="1001" then if mp3data_count_current_state="0000" or mp3data_count_current_state="1101" then MP3_SDO <= mp3data_reg(7); elsif mp3data_count_current_state="0001" then MP3_SDO <= mp3data_reg(6); elsif mp3data_count_current_state="0010" then MP3_SDO <= mp3data_reg(5); elsif mp3data_count_current_state="0011" then MP3_SDO <= mp3data_reg(4); elsif mp3data_count_current_state="0100" then MP3_SDO <= mp3data_reg(3); elsif mp3data_count_current_state="0101" then MP3_SDO <= mp3data_reg(2); elsif mp3data_count_current_state="0110" then MP3_SDO <= mp3data_reg(1); elsif mp3data_count_current_state="0111" then MP3_SDO <= mp3data_reg(0); else MP3_SDO <= '0'; end if; else --if mp3data_count_current_state="0000" or mp3data_count_current_state="1001" then if mp3data_count_current_state="0000" or mp3data_count_current_state="1101" then MP3_SDO <= mp3data_reg(0); elsif mp3data_count_current_state="0001" then MP3_SDO <= mp3data_reg(1); elsif mp3data_count_current_state="0010" then MP3_SDO <= mp3data_reg(2); elsif mp3data_count_current_state="0011" then MP3_SDO <= mp3data_reg(3); elsif mp3data_count_current_state="0100" then MP3_SDO <= mp3data_reg(4); elsif mp3data_count_current_state="0101" then MP3_SDO <= mp3data_reg(5); elsif mp3data_count_current_state="0110" then MP3_SDO <= mp3data_reg(6); elsif mp3data_count_current_state="0111" then MP3_SDO <= mp3data_reg(7); else MP3_SDO <= '0'; end if; end if; end if; end process; mp3data_count_state <= mp3data_count_current_state; --------------------- process(reset,clock,mp3data_count_current_state,mp3clk_state) begin if reset='1' then mp3_sdo_end <='0'; --elsif mp3dataclk='0' and mp3dataclk'event then elsif clock='1' and clock'event then if mp3data_count_current_state = "1001" and mp3clk_state="0011" then --if mp3data_count_current_state = "1100" and mp3clk_state="0011" then mp3_sdo_end <='1'; else mp3_sdo_end <='0'; end if; end if; end process; -------------------------- ---------------------------------------------------------------- process(reset,clock,mp3data_count_current_state,mp3clk_state,mp3reg_read_addr) begin if reset='1' then mp3reg_end_flag0 <='0'; elsif clock='1' and clock'event then if mp3reg_read_addr = "1000000000" and mp3data_count_current_state="1101" and mp3clk_state="0110" then mp3reg_end_flag0 <='1'; else mp3reg_end_flag0 <='0'; end if; end if; end process; process(reset,clock,mp3reg_end_flag0) begin if reset='1' then mp3reg_end_flag1 <= '0'; elsif clock='1' and clock'event then mp3reg_end_flag1 <= mp3reg_end_flag0; end if; end process; mp3reg_end_flag <= mp3reg_end_flag0 or mp3reg_end_flag1; mp3reg_read_end <= mp3reg_end_flag; MP3_SDO_end_flag <= mp3_sdo_end; ---------------------------------------------- End mp3_serial_out_a; --------------------------------------------------------------------------