Asia Pacific Technology Roadshow 2009

Date: August - November 2009 Region: Asia Pacific

Altera's Technology Roadshow will be held in China, India, Korea, Malaysia, Singapore, and Taiwan. You can get the complete event agenda, seminar abstract, and registration contacts below.

Seminars (1)

• LVDS/Transceiver Architecture and Features Enabled in Altera^® 40-nm Products
• Reduce Your 3-Gbps Transceiver Design Time with Altera Arria^® II GX FPGAs
• Designing Embedded Systems Easily and Quickly with FPGAs
• Building Video Systems Using the Altera Video Framework
• How DSP Builder Advanced Blockset Facilitates the Design of Wireless Systems
• High-Mobility, Low-Power Military Software Defined Radio Design
• Developing Industrial Systems with Altera Solutions
• Designing Low-Power, Cost-Optimized Remote-Radio-Units with Altera FPGAs
• Improving Your Time-to-Market by Using SDC Timing Constraints and TimeQuest Timing Analysis

Note:

1. Seminars vary between cities.

Event Schedule and Registration Contacts

India

Korea

Taiwan

Singapore

Malaysia

Seminar Abstracts

LVDS/Transceiver Architecture and Features Enabled in Altera 40-nm Products

Altera’s 40-nm FPGAs provide enhanced capabilities for field high-speed link applications. With soft-CDR technology, customers can build high-density HSSIO applications using 24-port Gigabit Ethernet (GbE) and other private protocols. The enhanced transceiver features, such as delay uncertainty, provide better support for the filed applications.

Reduce Your 3-Gbps Transceiver Design Time with Altera Arria II GX FPGAs

Transceiver design has many challenges, such as multiple design environments, limited design resources, time-to-market constraints, and strict power budgets. Arria II GX FPGAs can help you meet these challenges, reduce your design time, and complete your design easily for 3 Gbps. In this seminar, you will learn how to:

• Build a working PCIe design in 45 minutes
• Use a single design environment for increased productivity
• Minimize development time and costs using proven intellectual property (IP) and design examples
• Meet power budgets with the lowest power 3-Gbps FPGA

Designing Embedded Systems Easily and Quickly with FPGAs

Embedded systems design has challenges like cost and board size constraints, CPU obsolescence, short lead time, power constraints, and new feature requirements catering to market needs. FPGAs and the Nios^® II embedded soft RISC processor tackle these challenges by integrating external embedded devices within programmable logic devices (PLDs). In this seminar, you will learn how to create embedded systems implemented in programmable logic and to build a processor-based hardware system and run software on it. You will also see how quick and easy it is to build entire systems using Altera’s SOPC Builder tool to configure and integrate hardware IP blocks.

Building Video Systems Using the Altera Video Framework

High-definition video systems are increasingly adopting the FPGA fabric for design implementation. While implementing video systems on an FPGA provides the best price, power, and performance points, it also involves a complex design flow. Altera’s video framework is designed to minimize this design risk.

Altera is the only FPGA vendor that has developed a complete video design framework—which includes IP cores, an open video interface, reference designs, and development kits—designed to help you rapidly develop and prototype your video systems.

In this seminar, you will learn the basics of building an embedded video system in programmable logic. The seminar will introduce you to the video IP blocks, the system-level design tools, and the streaming video interface, and show you how to build a customizable video system that can be dynamically modified using an embedded processor.

How DSP Builder Advanced Blockset Facilitates the Design of Wireless Systems

As wireless design engineers strive to address ever-higher data rates in next-generation wireless systems, they are faced with some challenging requirements: both spectral efficiency and bandwidth must increase, and the cost per bit must be kept low. MIMO, OFDM, and TDD are multichannel technologies that show promise in meeting these objectives. Altera’s Advanced Blockset for DSP Builder provides unique synthesis technology that is optimized for these multichannel and customized designs, and provides fast design space exploration and effortless FPGA implementation. In this seminar, you will see how DSP Builder Advanced Blockset is used in Simulink from The MathWorks. You will also learn how to build multichannel finite impulse response (FIR) filters and see real example designs.

High-Mobility, Low-Power Military Software Defined Radio Design

The military community is transforming the battlefield of the 21st century around network-centric warfare. From satellite to soldier and everything in between, system size, weight, and power (SWaP) requirements are critical. Whether in manned (ships, aircraft, and vehicles) or unmanned (missiles, sensors, and air and ground vehicles (UAVs and UGVs)) equipment, secure wireless communications are central to the solution. Further, to cover multiple battlefield scenarios, add the complexity of triple-play (voice, video, and data) capabilities and multi-megabit bandwidth, the design challenges for secure communication devices are overwhelming. While airborne and maritime software-defined radios (SDRs) have functional and heat dissipation (cooling) challenges, the most demanding requirements for SWaP applications are in handheld, manpack, and small form factor (HMS) battery-operated systems.

Developing Industrial Systems with Altera Solutions

A growing array of industrial designs that require fast time-to-market and low-cost flexible solutions now use Altera FPGAs and CPLDs. From plant-wide automation, programmable logic controllers (PLCs), and I/O modules to servo drives and motion controllers, you can quickly modify products based on PLDs to support new functionalities while maintaining platform interoperability. In this seminar, you will learn how to build typical industrial platforms with Altera industrial solutions.

Designing Low-Power, Cost-Optimized Remote-Radio-Units with Altera FPGAs

Wireless network operators are putting greater emphasis on deploying low power, small form factor, and low-cost radio access equipment to minimize capital expenditures (CAPEX) and long-term operating expenses (OPEX). Faced with the challenges of meeting operators’ requirements, equipment vendors must choose suitable IC solutions that are low power, highly integrated (hence reduced form factor), and yet low cost when designing their products. Combined with easy-to-use software tools and IP, Altera offers a variety of system-on-a-chip (SOC) solutions that are particularly suited for remote radio head, wireless repeaters, and many other radio frequency (RF) applications. This seminar introduces you to Altera’s broad portfolio of 40-nm FPGAs and ASICs that are designed for low power, low cost, and high integration.

Improving Your Time to Market by using SDC Timing Constraints and TimeQuest Timing Analysis

In the 65-nm era and beyond, designers are faced with increasing design complexity challenges, which require a timing analysis tool with greater capabilities and flexibility. The Quartus^® II TimeQuest timing analyzer provides more powerful timing analysis features than other timing analysis tools in the industry. This tool offers benefits that improve time to market, including productive industry-standard Synopsys Design Constraint (SDC) support and simple reporting using industry-standard terminology. In this technical seminar, you will learn what the TimeQuest timing analyzer is and how it will help improve time-to-market. A TimeQuest timing analyzer demo will also be available for viewing.