January 1999
Department of Computer Science
University of Adelaide
GPO Box 498, Adelaide SA 5001
Australia
Phone: +61 8 303 4477
Fax: +61 8 303 4366
Email: petera@cs.adelaide.edu.au
WWW: http://www.cs.adelaide.edu.au/~petera
Australian citizen, born 2 March 1960, in North Adelaide, South Australia.
Ph.D., University of Adelaide, 1997. "An Experimental System for Evaluating Cache Coherence Protocols in Shared Memory Multiprocessors."
B.Sc. (Hons.) 1st class in Computer Science, University of Adelaide, 1983.
February 1998 - present: Senior Lecturer in Dept. Computer Science, University of Adelaide.
January 1997 - January 1998: Visiting Scholar at Dept ECECS, University of Cincinnati, USA.
July 1990 - February 1998: Lecturer in Dept. Computer Science, University of Adelaide.
1989 - June 1990: Principal Research Officer (Research Officer Grade 3) in Dept Computer Science, University of Adelaide. Duties included development of research objectives and strategies for the Leopard Multiprocessor Workstation Project, and project management for a team of four engineers and other support staff.
1984 - 1988: Senior Research Officer (Research Officer Grade 3) in Dept Computer Science, University of Adelaide. Duties included architectural design, detailed engineering design and simulation of prototype hardware for the Leopard Multiprocessor Workstation Project.
1983: Research Assistant in Leopard Multiprocessor Workstation Project in Dept Computer Science, University of Adelaide.
Advanced Computer Architecture (Honours/Masters)
Computer Architecture (level-3)
Computer Systems (level-2)
Programming and Data Structures (level-2)
Concepts of Computer Science (level-2)
Computer Systems (level-1)
Programming in Ada (level-1)
1995 - 1996: Key role in development of Bachelor of Computer Science and Bachelor of Engineering (IT&T) degree programs. Also participated in review of Bachelor of Science (Ma. & Comp. Sc.), Bachelor of Engineering (Electrical and Electronic Engineering) and Bachelor of Engineering (Computer Systems Engineering) degree programs.
1990 - present: Ongoing review and development of undergraduate Computer Science curriculum.
S. Tyerman, "High-Level Synthesis for Asynchronous Digital Systems" (PhD project, in progress)
N. Boroky, "GHDL: Tools for a Hardware Description Language" (1998)
C. Biggs, "SUAVE: Code Generation for Object-Oriented Extensions to VHDL" (1998)
M. Lodge, "Extending TyVIS to Support SUAVE" (1998)
K. Kerry, "STEVE: A Syntax-Directed Editor for VHDL" (1996)
M. Clarke, "VGE: A VHDL Graphical Editor" (1996)
M. Phillips, "A Syntax-Directed Editor for VHDL" (1994)
H. Detmold, "Concurrent VHDL Simulation" (1992)
W. S. McKeen, "Reducing the Execution Times of VHDL Simulations" (1992)
L. Willson, "Measuring Object Systems: An analysis of the Napier88 Persistent Object Store"
(1991)
1995: Secretary of the Centre for Computer Systems and Software Engineering.
1994 - 1996: Secretary of the Institute for Information Technology & Telecommunications
Steering Committee.
1993 - 1996: Member of the Board of the Centre for Computer Systems and Software
Engineering.
1992 - 1996: Information officer.
1991 - 1992, 1995 - : Member of Faculty of Engineering.
1991 - 1996: Member of Computer Systems Engineering Advisory Board.
1991 - 1996: Member of Computer Science curriculum review working group.
1990 - 1996: Level III course coordinator.
Parallel simulation algorithms for simulation of digital systems
Computer Aided Design tools, languages and techniques for digital systems
Computer architecture, in particular, memory hierarchies
Australian Research Council: "High Level Synthesis of Asynchronous Systems," with M. J. Liebelt (1999: $5,000)
University of Adelaide: "Concurrent Run-Time System for Simulation" (1992: $1700)
Australian Research Council: "Evaluation of Cache Coherence in Symmetric Multiprocessor Systems" (1988: $26,471; 1989: $28,685; 1990: $29,000; 1991: $30,000)
CSIRO: "The Leopard Workstation Project" (1988: $50,000; 1989: $50,000, 1990: $99,000; 1991: $44,500)
DSTO: "The Leopard Workstation Project" (1988: $30,000; 1989: $60,000; 1990: $30,000; 1991: $A61,000)
1997 - 1998: Program Chair for VIUF Fall '98 Conference.
1997 - 1998: Member of Program Committee for Forum for Design Languages '98.
1997 - 1998: Member of Program Committee for VIUF Spring '98 Conference.
1997: Expert Member of Program Committee for Design, Automation & Test in Europe.
1997: Member of program committee for VIUF Fall '97 Conference.
1997: Academic Representative on Committee of VIUF Mid-West Chapter.
1996: Member of program committee for VIUF Spring '97 Conference.
1995: Asia/Pacific Program Chair for 3rd International Conference on Electronic Hardware Description Languages.
1995 - present: member of IEEE Design Automation Standards Committee and various working groups.
1995: Member of program committee for VIUF Spring '95 Conference.
1994 - 1996: Consultant to Motorola Software Centre Australia.
1994: Tutorials Chair for 2nd International Conference on Electronic Hardware Description Languages.
1993 - 1994: Editor of Engineering Newsletter, Faculty of Engineering, Univerity of Adelaide.
1992 - 1993: Member of program and organizing committees for the First Asia Pacific Conference on Hardware Description Languages, Standards and Applications (December 1993)
1992: Presented external courses for Centre of Computer Systems and Software Engineering
1991: Developed and presented a two-day intensive course in VHDL for Austek Microsystems
1990 - present: Member of the board of the Centre for Computer Systems and Software Engineering, University of Adelaide.
1989: Consultant to Austek Microsystems' Advanced Development group.
1986 - 1988: Visits and research presentations to research groups and companies in USA, UK and Sweden.
1985 - 1988: Member of the IEEE P896.1 and P896.2 Futurebus Standard Working Groups, and P896.2 Cache Coherence Task Group.
1982: As part of VLSI design course, included a working experimental design on Australia's first Multi-project chip (AUSMPC-582).
1980 - 1981: Consultant for geophysics exploration equipment development.
IEE Proceedings Circuits, Devices and Systems (1999)
Prentice-Hall: Paul Foote and Fawn Engelmann, Verilog Revealed: A Practical Guide to System Simulation (1998)
Morgan Kaufmann: Ivan E. Sutherland, Robert E. Sproull and David L. Harris, Logical Effort: Designing Fast CMOS Circuits (1998)
Current Issues in Electronic Modeling (1996)
Third International Conference on Parallel Architectures and Compilation Techniques (1995)
Morgan Kaufmann: David Kaeli and Philip Sailer, The DLX Instruction Set Architecture Handbook (1994, 1995)
Prentice-Hall: David Pellerin, Electronic Design Automation: a User's Guide (1994); J. Bhasker, A Guide to VHDL Syntax (1994)
Fifth IEEE Symposium on Parallel and Distributed Processing (1993)
IFIP WG 10.3 (Concurrent Systems) Working Conference on Architectures and Compilation Techniques for Fine and Medium Grain Parallelism (1993)
ACM/IEEE International Symposium on Computer Architecture (1992)
Australian Software Engineering Conference (1991)
Australian Computer Science Conference and Australian Computer Science Communications
Australian Computer Journal
Senior Member of the Institute of Electrical & Electronic Engineers (IEEE)
Member of the Association for Computing Machinery (ACM)
Member of the Australian Computer Science Association
P. J. Ashenden, The Student's Guide to VHDL, Morgan Kaufmann Publishers, Inc. (San Francisco, California), ISBN 1-55860-520-7, 340 pp., 1998.
P. J. Ashenden, The Designer's Guide to VHDL, Morgan Kaufmann Publishers, Inc. (San Francisco, California), ISBN 1-55860-270-4, 668 pp., 1996.
P. J. Ashenden and P. A. Wilsey, "Considerations on Object-Oriented Extensions to VHDL," Proceedings of VHDL International Users Forum Spring-97 Conference, Santa Clara, California (April 1997), pp. 109-118. [Paper: PostScript, PDF. Slides: PostScript, PDF.]
P. J. Ashenden, Robert Esser and P. A. Wilsey, "Communication and Synchronization Using Bounded Channels in SUAVE," Proceedings of International Hardware Description Languages Conference, HDLCON '99, Santa Clara, California (April 1999), to appear. [Postscript, PDF]
P. J. Ashenden and P. A. Wilsey, "Protected Shared Variables in VHDL: IEEE Std 1076a," IEEE Design and Test of Computers (1999), to appear. [Postscript, PDF]
P. J. Ashenden and P. A. Wilsey, "Principles for Extensions to VHDL for High-Level Modeling," VLSI Design (1999), to appear. [Postscript, PDF]
P. J. Ashenden, P. A. Wilsey and D. E. Martin, "SUAVE: Object-Oriented and Genericity Extensions to VHDL for High-Level Modeling," Proceedings of Forum on Design Languages (FDL '98), Vol. 1, Lausanne, Switzerland (September 1998), pp. 93-102. [Postscript, PDF]
P. J. Ashenden and P. A. Wilsey, "Extensions to VHDL for Abstraction of Concurrency and Communication," Proceedings of Sixth International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS '98), Montreal, Canada (July 1998), pp. 301-308. [Postscript, PDF]
P. J. Ashenden, P. A. Wilsey and D. E. Martin, "SUAVE: Extending VHDL to Improve Modeling Support," IEEE Design and Test of Computers (April-June 1998), pp. 34-44. [Postscript, PDF]
P. J. Ashenden, "Modeling Digital Systems Using VHDL," IEEE Potentials (April/May 1998), pp. 27-30.
P. J. Ashenden and P. A. Wilsey, "Considerations on System-Level Behavioural and Structural Modeling Extensions to VHDL," Proceedings of VHDL International Users Forum Spring-98 Conference, Santa Clara, California (March 1998), pp. 42-50 (winner of Best Paper prize). [Postscript, PDF]
P. J. Ashenden and P. A. Wilsey, "A Comparison of Alternative Extensions for Data Modeling in VHDL," Proceedings of Hawai'i International Conference on System Sciences, Kona, Hawaii (January 1998). [Paper: Postscript, PDF. Slides: Postscript, PDF.]
P. J. Ashenden and P. A. Wilsey and Dale E. Martin, "SUAVE: Painless Extension for an Object-Oriented VHDL," Proceedings of VHDL International Users Forum Fall-97 Conference, Arlington, VA (October 1997), pp. 60-67. [PostScript, PDF]
P. J. Ashenden and P. A. Wilsey and Dale E. Martin, "Reuse Through Genericity in SUAVE," Proceedings of VHDL International Users Forum Fall-97 Conference, Arlington, VA (October 1997), pp. 170-177. [PostScript, PDF]
K. E. Kerry, P. J. Ashenden and M. J. Oudshoorn, "STEVE: A Syntax-Directed Editor for VHDL Based on SAVANT," Proceedings of VHDL International Users Forum Spring-97 Conference, Santa Clara, California (April 1997), pp. 71-78. [Paper: PostScript, PDF. Slides: PostScript, PDF.]
P. A. Wilsey, R. Vemuri, P. J. Ashenden and N. Mause, "Programmed Monitoring and Digital System Simulation," in J.-M. Bergé, O. Levia and J. Rouillard, Eds., Hardware/Software Co-Design and Co-Verification, Current Issues in Electronic Modeling, Vol. 8 (December 1996), pp. 145-162.
P. A. Wilsey, N. Mause, and P. J. Ashenden, "Abstract Data Types and the Digital System Description and Simulation Environments," in J.-M. Bergé, O. Levia and J. Rouillard, Eds., Hardware Component Modeling, Current Issues in Electronic Modeling, Vol. 5 (March 1996), pp. 33-53.
M. P. Phillips and P. J. Ashenden, "A Structure Editor for VHDL," Proceedings of VHDL International Users Forum Spring-95 Conference , San Diego, California (April 1995).
P. J. Ashenden and P. A. Wilsey, "Polymorphic Abstract Data Types in VHDL," 2nd International Conference on Electronic Hardware Description Languages (ICEHDL) , Las Vegas, Nevada (January 1995), pp. 35-40.
P. J. Ashenden, H. Detmold and W. S. McKeen, "Execution of VHDL Models using Parallel Discrete Event Simulation Algorithms," VLSI Design, Vol. 2, No. 1 (1994), pp. 1-16.
P. J. Ashenden, "A Comparision of Recursive and Repetitive Models of Recursive Hardware Structures," VHDL International Users Forum Spring '94 Conference , Oakland, California (May 1994), pp. 80-89.
P. J. Ashenden, H. Detmold and W. S. McKeen, "A centralized queue parallel simulator for VHDL," Proceedings of International Conference on Simulation and Hardware Description Languages, Tempe, Arizona (January 1994), pp. 161-166.
P. J. Ashenden, "Teaching Computer Architecture using VHDL," Proceedings of VHDL International Users Forum Fall-93 Conference, San Jose, California (October 1993), pp. 203-211.
P. J. Ashenden and C. D. Marlin, "A Behavioural Specification of Cache Coherence," Australian Computer Journal, Vol. 20, No. 2 (May 1988), pp. 50-57.
P. J. Cassidy, P. J. Ashenden and C. D. Marlin, "An Implementation of Modula-2 for Embedded Systems Development for NS32000," Australian Computer Science Communications, Vol. 8, No. 1 (February 1986), pp. 11-21.
P. J. Ashenden, C. J. Barter and C. D. Marlin, "A High Performance Workstation Design Employing Multiple Processors and Coherent Caching," Australian Computer Science Communications, Vol. 8, No. 1 (February 1986), pp. 335-345.
C. J. Barter, P. J. Ashenden, K. J. Maciunas and D. L. Knight, "The Design of a High Performance Workstation Computer," Australian Computer Science Communications, Vol. 6, No. 1 (February 1984), pp. 2-1 to 2-10.
P. J. Ashenden, C. J. Barter and C. D. Marlin, "The Leopard Workstation Project," ACM Computer Architecture News, Vol. 15, No. 4 (September 1987), pp. 40-51.
P. J. Ashenden, "Line Tap Aids Software Debugging", EDN (July 9, 1987), p. 268.
P. J. Ashenden, P. J. Cassidy and C. D. Marlin, "A Modula-2 Cross-compiler for NS32000," presented at MODUS meeting, San Francisco, California (June 1987).
P. J. Ashenden, C. J. Barter and C. D. Marlin, "Leopard: A Multiprocessor Workstation Design Employing Multiple Coherent Caches," Procedings of Seminar on Parallel Computing Architectures, (Telecom Research Laboratories, Clayton ,Victoria, February 1986) pp. 101-110.
D. L. Knight, P. J. Ashenden, C. D. Marlin and C. J. Barter, "The QDS-1000: A Modular Expandable Image Processing Workstation," presented at Remote Sensing - Current Status and Applications, South Australian Institute of Technology, Adelaide, South Australia (June 1985).
P. J. Ashenden, review of J. Mermet (ed.), VHDL for Simulation, Synthesis and Formal Proofs of Hardware, in Australian Computer Journal, Vol. 27, No. 1 (February 1995), pp. 35-36.
P. J. Ashenden, review of L. Baker, VHDL with Advanced Topics, Addison-Wesley, in IEEE Design & Test of Computers, Vol. 10, No. 4 (December 1993), pp. 6 & 96.
P. J. Ashenden and P. A. Wilsey, Proposed Extensions to VHDL for Abstraction of Concurrency and Communication, Joint Technical Report, TR-97-11, Dept. Computer Science, University of Adelaide, South Australia, and TR-210/12/97/ECECS, Department of Electrical and Computer Engineering and Computer Science, University of Cincinnati (December 1997). [PostScript, PDF]
P. J. Ashenden, P. A. Wilsey and D. E. Martin, SUAVE: A Proposal for Extensions to VHDL for High-Level Modeling, Joint Technical Report, TR-97-07, Dept. Computer Science, University of Adelaide, South Australia, and TR-207/08/97/ECECS, Department of Electrical and Computer Engineering and Computer Science, University of Cincinnati (August 1997). [PostScript, PDF]
P. J. Ashenden and P. A. Wilsey, Principles for Language Extension to VHDL to Support High-Level Modeling, Joint Technical Report TR-03/97, Dept. Computer Science, University of Adelaide, South Australia, and TR-204/05/97/ECECS, Department of Electrical and Computer Engineering and Computer Science, University of Cincinnati (May 1997). [PostScript, PDF]
P. J. Ashenden and P. A. Wilsey, A Comparison of Alternative Extensions for Data Modeling in VHDL, Joint Technical Report TR-02/97, Dept. Computer Science, University of Adelaide, South Australia, and TR-203/05/97/ECECS, Department of Electrical and Computer Engineering and Computer Science, University of Cincinnati (May 1997). [PostScript, PDF]
P. J. Ashenden, Implementing Polymorphic Abstract Data Types in VHDL , Technical Report 94-11 (June 1994), Dept. Computer Science, University of Adelaide, South Australia.
P. J. Ashenden, Recursive and Repetitive Hardware Models in VHDL, Joint Technical Report, TR 160/12/93/ECE, Department of Electrical and Computer Engineering, University of Cincinnati, and TR 93-19, Department of Computer Science, University of Adelaide, South Australia.
P. J. Ashenden, H. Detmold and W. S. McKeen, Parallel Execution of VHDL Models , Tech. Report 93-01 (January 1993), Dept. Computer Science, University of Adelaide, South Australia.
P. J. Ashenden, C. Fang, R. Gerhofer, K. R. Howard and G. C. Slater, The Leopard-2 General Data Processor Design Description, CCSSE Tech. Report LW-04 (March 1990), Dept. Computer Science, University of Adelaide, South Australia.
P. J. Ashenden, The Leopard-2 Futurebus Monitor Design Description, CCSSE Tech. Report LW-06 (March 1990), Dept. Computer Science, University of Adelaide, South Australia.
P. J. Ashenden, The Leopard-2 General Data Processor Local Memory Design Description , CCSSE Tech. Report LW-12 (March 1990), Dept. Computer Science, University of Adelaide, South Australia.
R. Gerhofer, C. Fang and P. J. Ashenden, The Leopard-2 Storage and Communications Processor Local Bus Description, CCSSE Tech. Report LW-19 (April 1990), Dept. Computer Science, University of Adelaide, South Australia.
P. J. Ashenden, The Leopard-2 Futurebus Interface Functional Description , CCSSE Tech. Report LW-10 (November 1989), Dept. Computer Science, University of Adelaide, South Australia.
P. J. Ashenden, C. J. Barter and M. A. Petty, The Leopard Multiprocessor Workstation Project, CCSSE Tech. Report LW-01 (November 1989), Dept. Computer Science, University of Adelaide, South Australia.
P. J. Ashenden, The Leopard-2 General Data Processor Local Bus Description , CCSSE Tech. Report LW-07 (September 1989), Dept. Computer Science, University of Adelaide, South Australia.
P. J. Ashenden, The Leopard-2 Futurebus Monitor Users Guide, CCSSE Tech. Report LW-05 (September 1989), Dept. Computer Science, University of Adelaide, South Australia.
P. J. Ashenden, R. Gerhofer and K. R. Howard, The Leopard-2 General Data Processor Users Guide, CCSSE Tech. Report LW-03 (September 1989), Dept. Computer Science, University of Adelaide, South Australia.
P. J. Ashenden, The Leopard-2 Workstation Bus Architecture, CCSSE Tech. Report LW-02 (August 1989), Dept. Computer Science, University of Adelaide, South Australia.
P. J. Ashenden, A Case Study in Programmable Logic Design, Tech. Report 88-01 (October 1988), Dept. Computer Science, University of Adelaide, South Australia.
P. J. Ashenden, Leopard-2 Hardware Architecture, Department of Computer Science, University of Adelaide, South Australia (October 1987).
P. J. Ashenden, L-Bus Specification, Version 1.2, Department of Computer Science, University of Adelaide, South Australia (November 1985; revised to Version 1.3, March 1986).
P. J. Ashenden, Leopard System Architecture, Version 1.0, Department of Computer Science, University of Adelaide, South Australia (August 1985; revised January 1987).
P. J. Ashenden, The VHDL Cookbook, Department of Computer Science, University of Adelaide, South Australia (July 1990).
P. J. Ashenden and P. A. Wilsey, "Extensions to VHDL for Abstraction of Concurrency and Communication",Proceedings of Forum on Design Languages (FDL '98), Vol. 2, Lausanne, Switzerland (September 1998), pp. 121-136.
P. J. Ashenden, Abstraction of Communication and Concurrency in VHDL, CERC/VIUF/IEEE Computer Society Workshop on 21st Century Electronic Systems Design: Breakthroughs in Quality and Productivity, Dayton, Ohio, December 1997. [Postscript, PDF]
P. J. Ashenden and P. A. Wilsey, Abstraction of Concurrency and Communication in VHDL, Third Workshop on System Level Design Languages, Barga, Italy, July 1997 [Abstract: Postscript, PDF. Slides: Postscript, PDF.]
P. J. Ashenden, P. A. Wilsey and D. E. Martin, SUAVE: Extending VHDL to Improve Modeling Support, Second Workshop on the Future of VHDL, Paris, France, July 1997 [Abstract: Postscript, PDF. Slides: Postscript, PDF.]
P. J. Ashenden and P. A. Wilsey, SUAVE: Extending VHDL to Improve Modeling Support, IEEE DASC OO-VHDL Study Group, Anaheim, California, June 1997. [PostScript, PDF]
P. J. Ashenden, "The Leopard Multiprocessor," First Australian Computer Architecture Workshop, Hobart, January 1992.
"SUAVE: Extending VHDL for Improve Support for High-Level Modeling"
- University of Adelaide, 1998
- Motorola Australia Software Centre, 1998
"SUAVE: Extending VHDL for High-Level System Modeling"
- University of Missouri-Rolla, 1997
"Cache Coherence in Multiprocessors"
- University of Adelaide, 1989, 1991
"The Future of Futurebus"
- Austek Microsystems, Adelaide, 1988
"The Leopard Multiprocessor Workstation"
- Silvar-Lisco Corp., Menlo Park CA, 1988
- AT&T Bell Laboratories, Holmdel NJ, 1988
- Lund University, Sweden, 1988
"Cache Coherence in the Leopard Multiprocessor Workstation"
- National Semiconductor Corp., Santa Clara CA, 1988
- Encore Computers, Inc, Marlboro MA, 1998
- University of St. Andrews, Scotland, 1988
P. J. Ashenden, M. Donaldson and C. Humphries, xdlx, a simulator for the DLX CPU with a graphical user interface.
P. J. Ashenden, dlxasm, an assembler for the DLX instruction set, derived from dlxsim from Stanford University.
P. J. Ashenden, dlx, a VHDL model suite describing the DLX CPU at behavioural and register transfer levels, and a test bench for the models.
P. J. Ashenden, recursive, a suite of recursive VHDL models, including a fanout tree and a fat tree interconnection network.