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-- Copyright Mentor Graphic Corporation 1991. 
-- All rights reserved.  
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--
--  Model Title:  clock generator
--  Date Created: 94/09/08 (THU)
--  Author:       T. Ohtsuka ( tootsuka@ss.titech.ac.jp )
--
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-- Model Description: 
--
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--
LIBRARY IEEE,ARITHMETIC ;
USE IEEE.STD_LOGIC_1164.ALL ;
USE ARITHMETIC.std_logic_arith.all ;

LIBRARY work ;
USE work.cpu_package.ALL ;

ENTITY cg IS
   PORT (
         clk1           :  OUT   STD_LOGIC ; -- 第1相クロック
         clk2           :  OUT   STD_LOGIC   -- 第2相クロック
        ) ;
END cg ;

-- ---------------------------------------------------------
--Copyright Mentor Graphic Corporation 1991.
--All rights reserved.
-- ---------------------------------------------------------
--Arch. Body for entity declared in 
------------------------------------------------------------
--
LIBRARY IEEE ;
LIBRARY work ;
 
USE IEEE.STD_LOGIC_1164.ALL ;
USE IEEE.STD_LOGIC_1164_EXTENSIONS.ALL ;
USE work.cpu_package.ALL ;

ARCHITECTURE behav1 OF cg IS

SIGNAL   ck    : STD_LOGIC :='0' ;   -- clock pulse from clock generater
SIGNAL   qs1,qs2 : STD_LOGIC :='0' ; -- 2 phase clock pulses

CONSTANT Period : TIME := 500 ns ;   -- クロックジェネレータの半周期

BEGIN

   clk_gen : PROCESS
   -- generate base clock by clock module IC
   BEGIN
      ck    <= NOT ck ;
      WAIT FOR Period ; -- the period is Period ns
   END PROCESS ;

   two_phase : PROCESS(ck)
   -- generate 2 phase clocks
   VARIABLE    q1,q2 : STD_LOGIC ;
   BEGIN
      q1 := qs1 ;
      q2 := qs2 ;
      IF P_rising(ck) THEN
         qs1 <= q2 ;
         qs2 <= NOT q1 ;
      END IF ;
      clk1 <= q1 NOR q2 ; -- generate phase 1 clock
      clk2 <= q1 AND q2 ; -- generate phase 2 clock
   END PROCESS ;

END behav1 ;