--------------------------------------------------
-- Model        :   8051 Behavioral Model,
--                  VHDL Entity mc8051.mc8051.symbol
--
-- Author       :   Michael Mayer (mrmayer@computer.org),
--                  Dr. Hardy J. Pottinger,
--                  Department of Electrical Engineering
--                  University of Missouri - Rolla
--
-- Created at   :   09/22/98 13:36:51
--
LIBRARY ieee ;
USE ieee.std_logic_1164.all;

ENTITY mc8051 IS
   PORT( 
      ea_n : IN     std_logic ;
      rst : IN     std_logic ;
      xtal1 : IN     std_logic ;
      ale : OUT    std_logic ;
      psen_n : OUT    std_logic ;
      xtal2 : OUT    std_logic ;
      P0 : INOUT  std_logic_vector( 7 DOWNTO 0 )  ;
      P1 : INOUT  std_logic_vector( 7 DOWNTO 0 )  ;
      P2 : INOUT  std_logic_vector( 7 DOWNTO 0 )  ;
      P3 : INOUT  std_logic_vector( 7 DOWNTO 0 ) 
   );

-- Declarations

END mc8051 ;
--
-- VHDL Architecture mc8051.mc8051.struct
--
-- Created:
--          by - mrmayer.UNKNOWN (eceultra3.ece.umr.edu)
--          at - 13:36:55 09/22/98
--
-- Generated by Mentor Graphics' Renoir(TM) 3.4 (Build 18)
--
LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
LIBRARY mc8051 ;
USE mc8051.synth_pack.all;

LIBRARY mc8051;

ARCHITECTURE struct OF mc8051 IS

-- Architecture declarations

-- Internal signal declarations
SIGNAL ac : std_logic;
SIGNAL ac_out : std_logic;
SIGNAL acc : std_logic_vector( 7 DOWNTO 0 ) ;
SIGNAL acknow : std_logic;
SIGNAL addr_gb : std_logic_vector( 7 DOWNTO 0 ) ;
SIGNAL cmp_true : std_logic;
SIGNAL cy : std_logic;
SIGNAL cy_out : std_logic;
SIGNAL cycle_states : std_logic_vector( 3 DOWNTO 0 ) ;
SIGNAL data_gb : std_logic_vector( 7 DOWNTO 0 ) ;
SIGNAL dec_rd_sp : std_logic;
SIGNAL dptr : std_logic_vector( 15 DOWNTO 0 ) ;
SIGNAL inc_wr_sp : std_logic;
SIGNAL indirect_sel : std_logic;
SIGNAL int_clk : std_logic;
SIGNAL int_rst : std_logic;
SIGNAL ir : std_logic_vector( 7 DOWNTO 0 ) ;
SIGNAL last_cycle : std_logic;
SIGNAL latch_pins : std_logic;
SIGNAL new_ir : std_logic;
SIGNAL ov : std_logic;
SIGNAL ov_out : std_logic;
SIGNAL p0_addr : std_logic_vector( 7 DOWNTO 0 ) ;
SIGNAL p0_ctrl : std_logic;
SIGNAL p2_addr : std_logic_vector( 7 DOWNTO 0 ) ;
SIGNAL p2_ctrl : std_logic;
SIGNAL parity : std_logic;
SIGNAL pdat_loc : std_logic_vector( 15 DOWNTO 0 ) ;
SIGNAL pdata : std_logic_vector( 7 DOWNTO 0 ) ;
SIGNAL rd_gb : std_logic;
SIGNAL rd_n : std_logic;
SIGNAL rd_n_ctrl : std_logic;
SIGNAL rd_pmem1 : std_logic;
SIGNAL rd_pmem2 : std_logic;
SIGNAL read_latch : std_logic;
SIGNAL rom_data : std_logic_vector( 7 DOWNTO 0 ) ;
SIGNAL rom_rd_n : std_logic;
SIGNAL rs : std_logic_vector( 1 DOWNTO 0 ) ;
SIGNAL rxd : std_logic;
SIGNAL rxd_ctrl : std_logic;
SIGNAL txd : std_logic;
SIGNAL txd_ctrl : std_logic;
SIGNAL wr_acc : std_logic;
SIGNAL wr_gb : std_logic;
SIGNAL wr_n : std_logic;
SIGNAL wr_n_ctrl : std_logic;
SIGNAL wr_out : std_logic;

-- Component Declarations
COMPONENT acc_reg
   PORT (
      addr_gb : IN     std_logic_vector( 7 DOWNTO 0 );
      indirect_sel : IN     std_logic;
      int_clk : IN     std_logic;
      int_rst : IN     std_logic;
      rd_gb : IN     std_logic;
      wr_acc : IN     std_logic;
      wr_gb : IN     std_logic;
      acc : OUT    std_logic_vector( 7 DOWNTO 0 );
      acknow : OUT    std_logic;
      parity : OUT    std_logic;
      data_gb : INOUT  std_logic_vector( 7 DOWNTO 0 )
   );
END COMPONENT;

COMPONENT b_sfr
   PORT (
      addr_gb : IN     std_logic_vector( 7 DOWNTO 0 );
      indirect_sel : IN     std_logic;
      int_clk : IN     std_logic;
      int_rst : IN     std_logic;
      rd_gb : IN     std_logic;
      wr_gb : IN     std_logic;
      acknow : OUT    std_logic;
      data_gb : INOUT  std_logic_vector( 7 DOWNTO 0 )
   );
END COMPONENT;

COMPONENT cpu_core
   PORT (
      ac : IN     std_logic;
      acc : IN     std_logic_vector( 7 DOWNTO 0 );
      acknow : IN     std_logic;
      cy : IN     std_logic;
      int_clk : IN     std_logic;
      int_rst : IN     std_logic;
      ir : IN     std_logic_vector( 7 DOWNTO 0 );
      new_ir : IN     std_logic;
      ov : IN     std_logic;
      rs : IN     std_logic_vector( 1 DOWNTO 0 );
      ac_out : OUT    std_logic;
      addr_gb : OUT    std_logic_vector( 7 DOWNTO 0 );
      cmp_true : OUT    std_logic;
      cy_out : OUT    std_logic;
      dec_rd_sp : OUT    std_logic;
      inc_wr_sp : OUT    std_logic;
      indirect_sel : OUT    std_logic;
      ov_out : OUT    std_logic;
      rd_gb : OUT    std_logic;
      rd_pmem1 : OUT    std_logic;
      rd_pmem2 : OUT    std_logic;
      read_latch : OUT    std_logic;
      wr_acc : OUT    std_logic;
      wr_gb : OUT    std_logic;
      wr_out : OUT    std_logic;
      data_gb : INOUT  std_logic_vector( 7 DOWNTO 0 )
   );
END COMPONENT;

COMPONENT dptr_reg
   PORT (
      addr_gb : IN     std_logic_vector( 7 DOWNTO 0 );
      indirect_sel : IN     std_logic;
      int_clk : IN     std_logic;
      int_rst : IN     std_logic;
      rd_gb : IN     std_logic;
      wr_gb : IN     std_logic;
      acknow : OUT    std_logic;
      dptr : OUT    std_logic_vector( 15 DOWNTO 0 );
      data_gb : INOUT  std_logic_vector( 7 DOWNTO 0 )
   );
END COMPONENT;

COMPONENT hi_dmem
   PORT (
      addr_gb : IN     std_logic_vector( 7 DOWNTO 0 );
      indirect_sel : IN     std_logic;
      int_clk : IN     std_logic;
      int_rst : IN     std_logic;
      rd_gb : IN     std_logic;
      wr_gb : IN     std_logic;
      acknow : OUT    std_logic;
      data_gb : INOUT  std_logic_vector( 7 DOWNTO 0 )
   );
END COMPONENT;

COMPONENT inter_ctrl
   PORT (
      P0 : IN     std_logic_vector( 7 DOWNTO 0 );
      acknow : IN     std_logic;
      cycle_states : IN     std_logic_vector( 3 DOWNTO 0 );
      dptr : IN     std_logic_vector( 15 DOWNTO 0 );
      ea_n : IN     std_logic;
      int_clk : IN     std_logic;
      int_rst : IN     std_logic;
      ir : IN     std_logic_vector( 7 DOWNTO 0 );
      last_cycle : IN     std_logic;
      pdat_loc : IN     std_logic_vector( 15 DOWNTO 0 );
      rom_data : IN     std_logic_vector( 7 DOWNTO 0 );
      rs : IN     std_logic_vector( 1 DOWNTO 0 );
      addr_gb : OUT    std_logic_vector( 7 DOWNTO 0 );
      ale : OUT    std_logic;
      indirect_sel : OUT    std_logic;
      p0_addr : OUT    std_logic_vector( 7 DOWNTO 0 );
      p0_ctrl : OUT    std_logic;
      p2_addr : OUT    std_logic_vector( 7 DOWNTO 0 );
      p2_ctrl : OUT    std_logic;
      pdata : OUT    std_logic_vector( 7 DOWNTO 0 );
      psen_n : OUT    std_logic;
      rd_gb : OUT    std_logic;
      rd_n : OUT    std_logic;
      rd_n_ctrl : OUT    std_logic;
      rom_rd_n : OUT    std_logic;
      wr_gb : OUT    std_logic;
      wr_n : OUT    std_logic;
      wr_n_ctrl : OUT    std_logic;
      data_gb : INOUT  std_logic_vector( 7 DOWNTO 0 )
   );
END COMPONENT;

COMPONENT lo_dmem
   PORT (
      addr_gb : IN     std_logic_vector( 7 DOWNTO 0 );
      int_clk : IN     std_logic;
      int_rst : IN     std_logic;
      rd_gb : IN     std_logic;
      wr_gb : IN     std_logic;
      acknow : OUT    std_logic;
      data_gb : INOUT  std_logic_vector( 7 DOWNTO 0 )
   );
END COMPONENT;

COMPONENT osc_sm
   PORT (
      int_clk : IN     std_logic;
      int_rst : IN     std_logic;
      xtal1 : IN     std_logic;
      cycle_states : OUT    std_logic_vector( 3 DOWNTO 0 );
      xtal2 : OUT    std_logic
   );
END COMPONENT;

COMPONENT p0_drv
   PORT (
      addr_gb : IN     std_logic_vector( 7 DOWNTO 0 );
      indirect_sel : IN     std_logic;
      int_clk : IN     std_logic;
      int_rst : IN     std_logic;
      latch_pins : IN     std_logic;
      p0_addr : IN     std_logic_vector( 7 DOWNTO 0 );
      p0_ctrl : IN     std_logic;
      rd_gb : IN     std_logic;
      read_latch : IN     std_logic;
      wr_gb : IN     std_logic;
      acknow : OUT    std_logic;
      P0 : INOUT  std_logic_vector( 7 DOWNTO 0 );
      data_gb : INOUT  std_logic_vector( 7 DOWNTO 0 )
   );
END COMPONENT;

COMPONENT p1_drv
   PORT (
      addr_gb : IN     std_logic_vector( 7 DOWNTO 0 );
      indirect_sel : IN     std_logic;
      int_clk : IN     std_logic;
      int_rst : IN     std_logic;
      latch_pins : IN     std_logic;
      rd_gb : IN     std_logic;
      read_latch : IN     std_logic;
      wr_gb : IN     std_logic;
      acknow : OUT    std_logic;
      P1 : INOUT  std_logic_vector( 7 DOWNTO 0 );
      data_gb : INOUT  std_logic_vector( 7 DOWNTO 0 )
   );
END COMPONENT;

COMPONENT p2_drv
   PORT (
      addr_gb : IN     std_logic_vector( 7 DOWNTO 0 );
      indirect_sel : IN     std_logic;
      int_clk : IN     std_logic;
      int_rst : IN     std_logic;
      latch_pins : IN     std_logic;
      p2_addr : IN     std_logic_vector( 7 DOWNTO 0 );
      p2_ctrl : IN     std_logic;
      rd_gb : IN     std_logic;
      read_latch : IN     std_logic;
      wr_gb : IN     std_logic;
      acknow : OUT    std_logic;
      P2 : INOUT  std_logic_vector( 7 DOWNTO 0 );
      data_gb : INOUT  std_logic_vector( 7 DOWNTO 0 )
   );
END COMPONENT;

COMPONENT p3_drv
   PORT (
      addr_gb : IN     std_logic_vector( 7 DOWNTO 0 );
      indirect_sel : IN     std_logic;
      int_clk : IN     std_logic;
      int_rst : IN     std_logic;
      latch_pins : IN     std_logic;
      rd_gb : IN     std_logic;
      rd_n : IN     std_logic;
      rd_n_ctrl : IN     std_logic;
      read_latch : IN     std_logic;
      rxd_ctrl : IN     std_logic;
      txd : IN     std_logic;
      txd_ctrl : IN     std_logic;
      wr_gb : IN     std_logic;
      wr_n : IN     std_logic;
      wr_n_ctrl : IN     std_logic;
      acknow : OUT    std_logic;
      rxd : OUT    std_logic;
      P3 : INOUT  std_logic_vector( 7 DOWNTO 0 );
      data_gb : INOUT  std_logic_vector( 7 DOWNTO 0 )
   );
END COMPONENT;

COMPONENT prog_rom
   PORT (
      int_clk : IN     std_logic;
      int_rst : IN     std_logic;
      p0_addr : IN     std_logic_vector( 7 DOWNTO 0 );
      p2_addr : IN     std_logic_vector( 7 DOWNTO 0 );
      rom_rd_n : IN     std_logic;
      rom_data : OUT    std_logic_vector( 7 DOWNTO 0 )
   );
END COMPONENT;

COMPONENT program_ctrl
   PORT (
      cmp_true : IN     std_logic;
      cycle_states : IN     std_logic_vector( 3 DOWNTO 0 );
      dptr : IN     std_logic_vector( 15 DOWNTO 0 );
      int_clk : IN     std_logic;
      int_rst : IN     std_logic;
      pdata : IN     std_logic_vector( 7 DOWNTO 0 );
      rd_pmem1 : IN     std_logic;
      rd_pmem2 : IN     std_logic;
      addr_gb : OUT    std_logic_vector( 7 DOWNTO 0 );
      dec_rd_sp : OUT    std_logic;
      inc_wr_sp : OUT    std_logic;
      indirect_sel : OUT    std_logic;
      ir : OUT    std_logic_vector( 7 DOWNTO 0 );
      last_cycle : OUT    std_logic;
      new_ir : OUT    std_logic;
      pdat_loc : OUT    std_logic_vector( 15 DOWNTO 0 );
      rd_gb : OUT    std_logic;
      wr_gb : OUT    std_logic;
      acknow : INOUT  std_logic;
      data_gb : INOUT  std_logic_vector( 7 DOWNTO 0 )
   );
END COMPONENT;

COMPONENT psw
   PORT (
      ac_out : IN     std_logic;
      addr_gb : IN     std_logic_vector( 7 DOWNTO 0 );
      cy_out : IN     std_logic;
      indirect_sel : IN     std_logic;
      int_clk : IN     std_logic;
      int_rst : IN     std_logic;
      ov_out : IN     std_logic;
      parity : IN     std_logic;
      rd_gb : IN     std_logic;
      wr_gb : IN     std_logic;
      wr_out : IN     std_logic;
      ac : OUT    std_logic;
      acknow : OUT    std_logic;
      cy : OUT    std_logic;
      ov : OUT    std_logic;
      rs : OUT    std_logic_vector( 1 DOWNTO 0 );
      data_gb : INOUT  std_logic_vector( 7 DOWNTO 0 )
   );
END COMPONENT;

COMPONENT serial
   PORT (
      addr_gb : IN     std_logic_vector( 7 DOWNTO 0 );
      indirect_sel : IN     std_logic;
      int_clk : IN     std_logic;
      int_rst : IN     std_logic;
      rd_gb : IN     std_logic;
      rxd : IN     std_logic;
      wr_gb : IN     std_logic;
      acknow : OUT    std_logic;
      rxd_ctrl : OUT    std_logic;
      txd : OUT    std_logic;
      txd_ctrl : OUT    std_logic;
      data_gb : INOUT  std_logic_vector( 7 DOWNTO 0 )
   );
END COMPONENT;

COMPONENT sp
   PORT (
      dec_rd_sp : IN     std_logic;
      inc_wr_sp : IN     std_logic;
      int_clk : IN     std_logic;
      int_rst : IN     std_logic;
      acknow : INOUT  std_logic;
      addr_gb : INOUT  std_logic_vector( 7 DOWNTO 0 );
      data_gb : INOUT  std_logic_vector( 7 DOWNTO 0 );
      indirect_sel : INOUT  std_logic;
      rd_gb : INOUT  std_logic;
      wr_gb : INOUT  std_logic
   );
END COMPONENT;


-- Optional embedded configurations
--synopsys translate_off
FOR ALL : acc_reg USE ENTITY mc8051.acc_reg;
FOR ALL : b_sfr USE ENTITY mc8051.b_sfr;
FOR ALL : cpu_core USE ENTITY mc8051.cpu_core;
FOR ALL : dptr_reg USE ENTITY mc8051.dptr_reg;
FOR ALL : hi_dmem USE ENTITY mc8051.hi_dmem;
FOR ALL : inter_ctrl USE ENTITY mc8051.inter_ctrl;
FOR ALL : lo_dmem USE ENTITY mc8051.lo_dmem;
FOR ALL : osc_sm USE ENTITY mc8051.osc_sm;
FOR ALL : p0_drv USE ENTITY mc8051.p0_drv;
FOR ALL : p1_drv USE ENTITY mc8051.p1_drv;
FOR ALL : p2_drv USE ENTITY mc8051.p2_drv;
FOR ALL : p3_drv USE ENTITY mc8051.p3_drv;
FOR ALL : prog_rom USE ENTITY mc8051.prog_rom;
FOR ALL : program_ctrl USE ENTITY mc8051.program_ctrl;
FOR ALL : psw USE ENTITY mc8051.psw;
FOR ALL : serial USE ENTITY mc8051.serial;
FOR ALL : sp USE ENTITY mc8051.sp;
--synopsys translate_on

BEGIN
-- Architecture concurrent statements
-- HDL Text Block 5
int_rst <= '0' WHEN rst='0' OR rst='L' ELSE
           '1' WHEN rst='1' OR rst='H';



-- HDL Text Block 6
int_clk <= xtal1;


-- HDL Text Block 7
latch_pins <= '1' WHEN cycle_states = s1p1 ELSE '0';


-- Instance port mappings.
   acc_reg1 : acc_reg
      PORT MAP (
         addr_gb => addr_gb(7 downto 0),
         indirect_sel => indirect_sel,
         int_clk => int_clk,
         int_rst => int_rst,
         rd_gb => rd_gb,
         wr_acc => wr_acc,
         wr_gb => wr_gb,
         acc => acc(7 downto 0),
         acknow => acknow,
         parity => parity,
         data_gb => data_gb(7 downto 0)
      );

   b_sfr1 : b_sfr
      PORT MAP (
         addr_gb => addr_gb(7 downto 0),
         indirect_sel => indirect_sel,
         int_clk => int_clk,
         int_rst => int_rst,
         rd_gb => rd_gb,
         wr_gb => wr_gb,
         acknow => acknow,
         data_gb => data_gb(7 downto 0)
      );

   I1 : cpu_core
      PORT MAP (
         ac => ac,
         acc => acc(7 downto 0),
         acknow => acknow,
         cy => cy,
         int_clk => int_clk,
         int_rst => int_rst,
         ir => ir(7 downto 0),
         new_ir => new_ir,
         ov => ov,
         rs => rs(1 downto 0),
         ac_out => ac_out,
         addr_gb => addr_gb(7 downto 0),
         cmp_true => cmp_true,
         cy_out => cy_out,
         dec_rd_sp => dec_rd_sp,
         inc_wr_sp => inc_wr_sp,
         indirect_sel => indirect_sel,
         ov_out => ov_out,
         rd_gb => rd_gb,
         rd_pmem1 => rd_pmem1,
         rd_pmem2 => rd_pmem2,
         read_latch => read_latch,
         wr_acc => wr_acc,
         wr_gb => wr_gb,
         wr_out => wr_out,
         data_gb => data_gb(7 downto 0)
      );

   dptr1 : dptr_reg
      PORT MAP (
         addr_gb => addr_gb(7 downto 0),
         indirect_sel => indirect_sel,
         int_clk => int_clk,
         int_rst => int_rst,
         rd_gb => rd_gb,
         wr_gb => wr_gb,
         acknow => acknow,
         dptr => dptr(15 downto 0),
         data_gb => data_gb(7 downto 0)
      );

   hi_dmem1 : hi_dmem
      PORT MAP (
         addr_gb => addr_gb(7 downto 0),
         indirect_sel => indirect_sel,
         int_clk => int_clk,
         int_rst => int_rst,
         rd_gb => rd_gb,
         wr_gb => wr_gb,
         acknow => acknow,
         data_gb => data_gb(7 downto 0)
      );

   inter_ctrl1 : inter_ctrl
      PORT MAP (
         P0 => P0(7 downto 0),
         acknow => acknow,
         cycle_states => cycle_states(3 downto 0),
         dptr => dptr(15 downto 0),
         ea_n => ea_n,
         int_clk => int_clk,
         int_rst => int_rst,
         ir => ir(7 downto 0),
         last_cycle => last_cycle,
         pdat_loc => pdat_loc(15 downto 0),
         rom_data => rom_data(7 downto 0),
         rs => rs(1 downto 0),
         addr_gb => addr_gb(7 downto 0),
         ale => ale,
         indirect_sel => indirect_sel,
         p0_addr => p0_addr(7 downto 0),
         p0_ctrl => p0_ctrl,
         p2_addr => p2_addr(7 downto 0),
         p2_ctrl => p2_ctrl,
         pdata => pdata(7 downto 0),
         psen_n => psen_n,
         rd_gb => rd_gb,
         rd_n => rd_n,
         rd_n_ctrl => rd_n_ctrl,
         rom_rd_n => rom_rd_n,
         wr_gb => wr_gb,
         wr_n => wr_n,
         wr_n_ctrl => wr_n_ctrl,
         data_gb => data_gb(7 downto 0)
      );

   lo_dmem1 : lo_dmem
      PORT MAP (
         addr_gb => addr_gb(7 downto 0),
         int_clk => int_clk,
         int_rst => int_rst,
         rd_gb => rd_gb,
         wr_gb => wr_gb,
         acknow => acknow,
         data_gb => data_gb(7 downto 0)
      );

   osc : osc_sm
      PORT MAP (
         int_clk => int_clk,
         int_rst => int_rst,
         xtal1 => xtal1,
         cycle_states => cycle_states(3 downto 0),
         xtal2 => xtal2
      );

   p0_drv1 : p0_drv
      PORT MAP (
         addr_gb => addr_gb(7 downto 0),
         indirect_sel => indirect_sel,
         int_clk => int_clk,
         int_rst => int_rst,
         latch_pins => latch_pins,
         p0_addr => p0_addr(7 downto 0),
         p0_ctrl => p0_ctrl,
         rd_gb => rd_gb,
         read_latch => read_latch,
         wr_gb => wr_gb,
         acknow => acknow,
         P0 => P0(7 downto 0),
         data_gb => data_gb(7 downto 0)
      );

   p1_drv1 : p1_drv
      PORT MAP (
         addr_gb => addr_gb(7 downto 0),
         indirect_sel => indirect_sel,
         int_clk => int_clk,
         int_rst => int_rst,
         latch_pins => latch_pins,
         rd_gb => rd_gb,
         read_latch => read_latch,
         wr_gb => wr_gb,
         acknow => acknow,
         P1 => P1(7 downto 0),
         data_gb => data_gb(7 downto 0)
      );

   p2_drv1 : p2_drv
      PORT MAP (
         addr_gb => addr_gb(7 downto 0),
         indirect_sel => indirect_sel,
         int_clk => int_clk,
         int_rst => int_rst,
         latch_pins => latch_pins,
         p2_addr => p2_addr(7 downto 0),
         p2_ctrl => p2_ctrl,
         rd_gb => rd_gb,
         read_latch => read_latch,
         wr_gb => wr_gb,
         acknow => acknow,
         P2 => P2(7 downto 0),
         data_gb => data_gb(7 downto 0)
      );

   p3_drv1 : p3_drv
      PORT MAP (
         addr_gb => addr_gb(7 downto 0),
         indirect_sel => indirect_sel,
         int_clk => int_clk,
         int_rst => int_rst,
         latch_pins => latch_pins,
         rd_gb => rd_gb,
         rd_n => rd_n,
         rd_n_ctrl => rd_n_ctrl,
         read_latch => read_latch,
         rxd_ctrl => rxd_ctrl,
         txd => txd,
         txd_ctrl => txd_ctrl,
         wr_gb => wr_gb,
         wr_n => wr_n,
         wr_n_ctrl => wr_n_ctrl,
         acknow => acknow,
         rxd => rxd,
         P3 => P3(7 downto 0),
         data_gb => data_gb(7 downto 0)
      );

   I2 : prog_rom
      PORT MAP (
         int_clk => int_clk,
         int_rst => int_rst,
         p0_addr => p0_addr(7 downto 0),
         p2_addr => p2_addr(7 downto 0),
         rom_rd_n => rom_rd_n,
         rom_data => rom_data(7 downto 0)
      );

   I0 : program_ctrl
      PORT MAP (
         cmp_true => cmp_true,
         cycle_states => cycle_states(3 downto 0),
         dptr => dptr(15 downto 0),
         int_clk => int_clk,
         int_rst => int_rst,
         pdata => pdata(7 downto 0),
         rd_pmem1 => rd_pmem1,
         rd_pmem2 => rd_pmem2,
         addr_gb => addr_gb(7 downto 0),
         dec_rd_sp => dec_rd_sp,
         inc_wr_sp => inc_wr_sp,
         indirect_sel => indirect_sel,
         ir => ir(7 downto 0),
         last_cycle => last_cycle,
         new_ir => new_ir,
         pdat_loc => pdat_loc(15 downto 0),
         rd_gb => rd_gb,
         wr_gb => wr_gb,
         acknow => acknow,
         data_gb => data_gb(7 downto 0)
      );

   psw1 : psw
      PORT MAP (
         ac_out => ac_out,
         addr_gb => addr_gb(7 downto 0),
         cy_out => cy_out,
         indirect_sel => indirect_sel,
         int_clk => int_clk,
         int_rst => int_rst,
         ov_out => ov_out,
         parity => parity,
         rd_gb => rd_gb,
         wr_gb => wr_gb,
         wr_out => wr_out,
         ac => ac,
         acknow => acknow,
         cy => cy,
         ov => ov,
         rs => rs(1 downto 0),
         data_gb => data_gb(7 downto 0)
      );

   serial1 : serial
      PORT MAP (
         addr_gb => addr_gb(7 downto 0),
         indirect_sel => indirect_sel,
         int_clk => int_clk,
         int_rst => int_rst,
         rd_gb => rd_gb,
         rxd => rxd,
         wr_gb => wr_gb,
         acknow => acknow,
         rxd_ctrl => rxd_ctrl,
         txd => txd,
         txd_ctrl => txd_ctrl,
         data_gb => data_gb(7 downto 0)
      );

   sp1 : sp
      PORT MAP (
         dec_rd_sp => dec_rd_sp,
         inc_wr_sp => inc_wr_sp,
         int_clk => int_clk,
         int_rst => int_rst,
         acknow => acknow,
         addr_gb => addr_gb(7 downto 0),
         data_gb => data_gb(7 downto 0),
         indirect_sel => indirect_sel,
         rd_gb => rd_gb,
         wr_gb => wr_gb
      );


END struct;