Microsystems Prototyping Laboratory

aof2201: 2 / 2 AND / OR MUX

• Gate Level Schematic
• Transistor Level Schematic
• Layout
• Logic Equation
• Inputs
• Outputs
• Truth Table
• Terminal Location and Capacitance
• Characterization Data

here.

---------------------------------
A	B	C	D	O
---------------------------------
1	1	x	x	1
x	x	1	1	1
0	x	0	x	0
0	x	x	0	0
x	0	0	x	0
x	0	x	0	0
---------------------------------

--------------------------------------------
Name	X_loc	Y_loc	   Capacitance (fF)
	lambda  lambda   2U	1.2U	0.8U
--------------------------------------------
A1	54.25	28	66.2	31.9	26.2
B1	33	29	62.4	30.6	25.2
C2	20	22	58.3	28.4	24.3
D2	4.95	23.9	66.7	31.9	26.5
O	72	25.5	-	-	-
--------------------------------------------

• Delay Information