Microsystems Prototyping Laboratory

aof3201: 3 / 2 AND / OR MUX

• Gate Level Schematic
• Transistor Level Schematic
• Layout
• Logic Equation
• Inputs
• Outputs
• Truth Table
• Terminal Location and Capacitance
• Characterization Data

here.

-------------------------------------------------
A	B	C	D	E	F	O
-------------------------------------------------
1	1	x	x	x	x	1
x	x	1	1	x	x	1
x	x	x	x	1	1	1
0	x	0	x	0	x	0
0	x	0	x	x	0	0
0	x	x	0	0	x	0
0	x	x	0	x	0	0
x	0	0	x	0	x	0
x	0	0	x	x	0	0
x	0	x	0	0	x	0
x	0	x	0	x	0	0
-------------------------------------------------

--------------------------------------------
Name	X_loc	Y_loc	   Capacitance (fF)
	lambda  lambda   2U	1.2U	0.8U
--------------------------------------------
A1	4.85	23.65	65.8	31.1	25.7
B1	16	26	56.4	27.2	23.1
C2	33	29	59.2	28.8	23.8
D2	56	31	61.7	29.4	24.5
E3	87.05	30.5	63.8	30.4	25.3
F3	105.05	26	59.6	28.9	24.1
O	72.5	29	-	-	-
--------------------------------------------

• Delay Information