Microsystems Prototyping Laboratory

blf00401: 2 / 2 OR / NAND / AND MUX

• Gate Level Schematic
• Transistor Level Schematic
• Layout
• Logic Equation
• Inputs
• Outputs
• Truth Table
• Terminal Location and Capacitance
• Characterization Data

here.

---------------------------------
A	B	C	D	O
---------------------------------
0	0	x	x	0
x	x	1	1	0
1	x	0	x	1
1	x	x	0	1
x	1	0	x	1
x	1	x	0	1
---------------------------------

--------------------------------------------
Name	X_loc	Y_loc	   Capacitance (fF)
	lambda  lambda   2U	1.2U	0.8U
--------------------------------------------
A1	50	18	65.0	32.3	27.4
B1	63	20.05	69.5	34.4	28.8
C2	24.5	31	62.1	30.8	25.8
D2	7	28	66.7	32.5	27.2
O	82.45	24	-	-	-
--------------------------------------------

• Delay Information