Microsystems Prototyping Laboratory

blf00601: 3 / 2 AND / OR MUX

• Gate Level Schematic
• Transistor Level Schematic
• Layout
• Logic Equation
• Inputs
• Outputs
• Truth Table
• Terminal Location and Capacitance
• Characterization Data

here.

---------------------------------
A	B	C	D	O
---------------------------------
1	1	x	x	1
x	x	1	x	1
x	x	x	1	1
0	x	0	0	0
x	0	0	0	0
---------------------------------

--------------------------------------------
Name	X_loc	Y_loc	   Capacitance (fF)
	lambda  lambda   2U	1.2U	0.8U
--------------------------------------------
A1	6.5	23.5	66.1	31.8	22.7
B1	16	23.5	61.6	30.2	21.9
C2	58	21	68.8	33.9	25.1
D2	77	21	67.2	33.3	24.5
O	46	25.5	-	-	-
--------------------------------------------

• Delay Information