Microsystems Prototyping Laboratory

dfrf301: D-FF W / RST & Q

Gate Level Schematic of the standard cell "dfrf301".

Schematic of the standard cell "dfrf301" with device sizes in lambda.

Layout of the standard cell "dfrf301"

here.

Logic Equation: Q = [(Qn-1 * CLK2) + (DATA1n-1) * CLK2')] * RST3

Input(s): CLK2, DATA1, RST3

Output(s): Q

Truth Table 

--------------------------------
CLK	DATA	RST	Q
--------------------------------
l2h	x	1	Qn-1
h2l	x	1	DATA1
x	x	0	0
--------------------------------

Terminal Location and Capacitance Table 

--------------------------------------------
Name	X_loc	Y_loc	   Capacitance (fF)
	lambda  lambda   2U	1.2U	0.8U
--------------------------------------------
CLK2	11.5	22	62.8	29.0	18.9
DATA1	49	39	58.4	28.8	18.4
Q	212	31.5	-	-	-
RST3	123	20	89.8	37.1	23.0
--------------------------------------------

Characterization Data