Microsystems Prototyping Laboratory

invf161: ENABLED INVERTER W / SET & RST

• Gate Level Schematic
• Transistor Level Schematic
• Layout
• Logic Equation
• Inputs
• Outputs
• Truth Table
• Terminal Location and Capacitance
• Characterization Data

here.

-----------------------------------------
EN	DATA	SET	RST	O
-----------------------------------------
0	0	0	0	1
0	0	0	1	+
0	0	1	0	Z
0	0	1	1	0
0	1	0	0	1
0	1	0	1	+
0	1	1	0	Z
0	1	1	1	0
1	0	0	0	1
1	0	0	1	+
1	0	1	0	1
1	0	1	1	0
1	1	0	0	1
1	1	0	1	+
1	1	1	0	0
1	1	1	1	0
-----------------------------------------

--------------------------------------------
Name	X_loc	Y_loc	   Capacitance (fF)
	lambda  lambda   2U	1.2U	0.8U
--------------------------------------------
DATA1	32	28	68.2	33.1	21.9
EN2	7.5	20	77.8	36.3	23.0
O	58	18	-	-	-
RST3	40	37	59.3	29.1	19.6
SET4	50	29	73.2	35.2	22.9
--------------------------------------------

• Delay Information