Microsystems Prototyping Laboratory

lgnf321: D-LATCH W / ACTIVE LOW CLK & HI-Z OUTPUT

• Gate Level Schematic
• Transistor Level Schematic
• Layout
• Logic Equation
• Inputs
• Outputs
• Truth Table
• Terminal Location and Capacitance
• Characterization Data

here.

Hi-Z when EN3 = 0

-------------------------------
CLK	DATA	EN	Q
-------------------------------
1	x	1	Qn-1
0	0	1	0
0	1	1	1
x	x	0	Z
-------------------------------

--------------------------------------------
Name	X_loc	Y_loc	   Capacitance (fF)
	lambda  lambda   2U	1.2U	0.8U
--------------------------------------------
CLK2	34	28	75.7	54.7	37.6
DATA1	5	29.5	73.9	60.1	40.1
EN3	172	26	62.2	50.3	33.4
Q	138	37.25	-	-	-
--------------------------------------------

• Delay Information
• Hold Time Information
• Setup Time Information