Microsystems Prototyping Laboratory

lgsf311: D - LATCH W /SET & ACTIVE LOW CLK

Gate Level Schematic of the standard cell "lgsf311".

Schematic of the standard cell "lgsf311" with device sizes in lambda.

Layout of the standard cell "lgsf311"

here.

Logic Equation: Q = [(Qn-1 * CLK2) + (DATA1 * CLK2')] + SET4'

Input(s): CLK2, DATA1, SET4

Output(s): Q, Q_b

Truth Table 

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Terminal Location and Capacitance Table 

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Name	X_loc	Y_loc	   Capacitance (fF)
	lambda  lambda   2U	1.2U	0.8U
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CLK2	42	40.5	78.5	54.1	46.5
DATA1	4.5	21	73.9	51.0	51.1
Q	139	26.5	-	-	-
Q_b	115	26	-	-	-
SET4	50.5	27	77.3	58.8	49.5
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Characterization Data