Microsystems Prototyping Laboratory

nanf301: 3 INPUT NAND

• Gate Level Schematic
• Transistor Level Schematic
• Layout
• Logic Equation
• Inputs
• Outputs
• Truth Table
• Terminal Location and Capacitance
• Characterization Data

here.

-------------------------
A	B	C	O
-------------------------
0	x	x	1
x	0	x	1
x	x	0	1
1	1	1	0
-------------------------

--------------------------------------------
Name	X_loc	Y_loc	   Capacitance (fF)
	lambda  lambda   2U	1.2U	0.8U
--------------------------------------------
A1	6	26	72.5	34.5	22.7
B1	18.5	29	69.1	33.0	21.8
C1	37.5	25	67.9	32.3	20.9
O	28	38.5	-	-	-
--------------------------------------------

• Delay Information