Microsystems Prototyping Laboratory

norf301: 3 INPUT NOR

• Gate Level Schematic
• Transistor Level Schematic
• Layout
• Logic Equation
• Inputs
• Outputs
• Truth Table
• Terminal Location and Capacitance
• Characterization Data

here.

-------------------------
A	B	C	O
-------------------------
0	0	0	1
x	x	1	0
x	1	x	0
1	x	x	0
-------------------------

--------------------------------------------
Name	X_loc	Y_loc	   Capacitance (fF)
	lambda  lambda   2U	1.2U	0.8U
--------------------------------------------
A1	40	24	65.9	33.7	28.8
B1	19.1	23.95	68.0	34.6	29.7
C1	5.7	23.9	71.0	35.8	30.3
O	31	23.9	-	-	-
--------------------------------------------

• Delay Information