Microsystems Prototyping Laboratory

slrf310: SCAN LATCH W / RST & ACTIVE LOW CLOCK

• Gate Level Schematic
• Transistor Level Schematic
• Layout
• Logic Equation
• Inputs
• Outputs
• Truth Table
• Terminal Location and Capacitance
• Characterization Data

here.

---------------------------------------------------------------------------
CLK2	EN,ENb	Ti	DATA1	RST3	Q	Q_b	1
---------------------------------------------------------------------------
x	x	x	1	Qn-1	Q_bn-1	0	0,1
x	x	1	DATA1	DATA1'	0	1,0	x
x	1	Ti	Ti'	x	x	x	x
0	0	1	
---------------------------------------------------------------------------

--------------------------------------------
Name	X_loc	Y_loc	   Capacitance (fF)
	lambda  lambda   2U	1.2U	0.8U
--------------------------------------------
CLK2	13	25	51.5	23.8	19.9
DATA1	82	35	50.0	24.1	19.4
ENTEST	72	35	-	-	-
ENTESTb	125	15	-	-	-
Q	118.5	27	-	-	-
Q_b	143.5	29.5	-	-	-
RST3	153	40	70.1	33.0	27.4
TESTin	107	15	-	-	-
--------------------------------------------

• Delay Information
• Hold Time Information
• Setup Time Information