Microsystems Prototyping Laboratory

Static RAM Generation Tool

Overview

The Static RAM Generator was designed for speed and ease in the VHDL modeling of Static RAMS with various address bus widths, data bus widths, and control functions.

Three files will be generated and delivered via a dialog box: an entity, an architecture, and a data file. If a data file is uploaded, it will be written out again to a file of the same name as the file that was submitted.

General Statement: All control signals (Output Enable, Write Enable, and Chip Enable) are assumed to be active HIGH. Also note that write-through functionality is not supported.

Each field header on the form is linked to its corresponding section in the help document.

Examples:

NEC uPD4016 2048 x 8-BIT SRAM
Cypress CY7C199 32K x 8-BIT SRAM
Motorola MCM6229 256K x 4-BIT SRAM
Motorola MCM6207 256K x 1-BIT SRAM w/ Separate I/O
Micron MT5C2564 64K x 4 FAST SRAM
Micron MT5C6406 16K x 4 FAST SRAM w/ Separate I/O and Multiple Chip Select

entity name			architecture name
address width			data width
output enable function			shared I/O YES NO
write enable function			X generation TRUE FALSE
chip enable function			message generation TRUE FALSE
trc	taa	toha	tace	tdoe	tlzoe
thzoe	tlzce	thzce	twc	tsce	taw
tha	tsa	tpwe	tsd	thd	thzwe
tlzwe	data file