fetch.vhd

'Fetch' stage control, 1st stage in the five-stage pipeline
Output of this stage is the state for the decode stage
Internal FSM is used to handle insertion of trap op into instruction stream to handle an interrupt.

IRload

load line for the Instruction Register (IR)

PCload

load for the Program Counter (PC)

DecodeState

'state' output for the decode stage FSM. The decode state FSM is simple, only has two states