pc.vhd

This is the vhdl code for the synthesis of the program counter module

selects a constant value to be gated to S2 bus

load line for instruction reg

Contains the 5-bit address of the destination register

Contains the 5-bit opcode

Indicates the AlU operation

Output enable of the temporary instruction register when its output is connected to the S1bus or S2bus respectively

controls sign extension of the immediate value

Output enable of the Instuction Address Register

Load line for the Program Counter Register

Select signal for the PC multiplexer which controls the input to the PC

Contains the output of the ALU

Contains the previous output of the ALU i.e. the output of the MEM stage

Contains the previous output of the memory stage i.e. the output of the write back stage

Output of the LMD register

Prevents the start of the Instruction Memory cycle. ???

Indicates start of memory cycle

Wait signal from the instruction memory

Wait signal to the rest of the DLX stages

Prevents write in the memory stage

Inhibits write in the write back stage