Interface
Inputs
- clk, reset
- low_ld - load LOW value; will be taken from address bus
- low_high - load HIGH value; will be taken from address bus
- DIN[7..0] Data bus to RAM
- Addr[5..0] Address bus to RAM.
- Zero - start a zero cycle
Outputs
- DOUT[7..0]
- Busy - when assert, busy zeroing RAM