EE 4743 – Homework #1 - FPGA Families

Due Monday, Feb 8th, Classtime

 

Answer the following questions about FPGA families. Use whatever resources you need – I have placed links to the companies and data sheets on the EE 4743 WWW page (www.erc.msstate.edu/~reese/EE4743 / Here)

For the Actel MX, Xilinx Virtex, and Altera Flex10K families answer the following (put your answers in a tabular format so that the different families can be easily compared). Your report must be typed. Turn in a hardcopy of your report at class time.

YOU MAY NOT WORK TOGETHER!! This must be YOUR OWN WORK! Any violations will be treated as an academic dishonesty case!

WWW sites of interest (www.xilinx.com, www.altera.com, www.actel.com ).

  1. What is the maximum number of gates claimed for each family?
  2. What is the maximum number of logic elements (as defined by the family) available?
  3. Do the families offer monolithic SRAM blocks on board ? (SRAM blocks that are standalone – not SRAM build from lookup tables).
  4. What is the maximum number of SRAM bits from monolithic SRAM blocks?
  5. Are the monolithic SRAM blocks dual ported? (dual ported means that I can be reading from one address while writing to another address).
  6. What are the maximum number of global clock signals supported?
  7. Does the family support any type of low voltage, high speed IO? (i.e., GTL, HSTL, etc.)
  8. What is the lowest power supply voltage supported?
  9. What is maximum package size supported (give the TYPE and number of pins supported). Type would be PGA, Quadflat pack, BGA, etc.
  10. Is there is there an ability to generate a clock on chip or do I need an external clock source?
  11. Is there a Phased Locked Loop or Delay Locked Loop module on chip? If YES, then what is the maximum clock multiplier that I can use for an off –chip clock?
  12. Are there any other special resources on board? High Speed decoders? Dedicated ALUs? Others?
  13. Can I implement on-chip tri-state busses? To do this, I must have the ability to implement a tri-state buffer on the chip.
  14. What is the minimum Pin-to-Pin delay claimed for the family?

 

Give a brief summary of an FPGA family OTHER than the families mentioned above. You may NOT use other device families from Actel, Xilinx, or Altera with the following exception: from Xilinx, you may look at the XC6200 family. A good place to start looking for other FPGA vendors is the Xilinx home page – click on the "Smart Search" button – this brings you to a page that lists other FPGA vendors.

Your summary should be approximately one page and should discuss the questions above in addition to discussing the basic logic cell architecture, basic routing architecture. Include graphics on a 2nd page that shows the logic cell architecture and global architecture.