Compute the following timings:

1. Minimum Pin to Pin delay (through input pin, through one combinational logic element, through one output pin.)
2. Minimum Register to Register Delay (From clock input pin, through global net . through Clock to Q delay through DFF of a logic element, through one combinational logic element to setup time on DFF input).
3. Minimum Clock to Out delay (From clock input pin, through global net, through Clock to Q of a logic element DFF, through an output pin).
4. Minimum input setup time (through input pin to D input of a DFF inside of a logic element). Be sure to account for the delay of the external clock to internal clock pin of the DFF.
5. Compute the minimum clock frequency of a two-chip system based upon the minimum clock-to-out timing and minimum setup input setup time.

Answer these questions for the Altera Flex 10K (use the EPF10K20 device numbers) and Xilinx Virtex families. In the above timings, a combinational logic element means one LUT. A "pin" means the logic associated with an IO pin. In Altera terminology this is an "IO Element", in Xilinx terminology this is an "Input/Output Buffer (IOB)".

Use the data sheets for these families on the class WWW site, and use the timing models that are contained in the data sheets. Use the fastest speed grade possible. The Xilinx datasheet does not provide an overall timing model – just detailed timing on the IOB (input output buffer) and CLB (configurable logic block). You will need to refer to the detailed diagrams of the CLB and IOB to understand the timings. Include routing delays if they are specified in the timing model. With the Xilinx Virtex device, be sure that you read the description of the DLL operation and understand its effect on clock delay (this important in questions 2, 3, 4).

You DO NOT have to use any environmental derating factors. Just use the datasheet numbers for the best speed grade possible.

To get any credit for this assignment you MUST show the timing equation that you are using to compute the delays, the names of each timing element and given in the appropriate data sheet, and the delay contribution of each element. If you simply give me numbers as the answers without showing all of your work, then you will get zero credit.