To Do 

Needed Files:

Testing the Design

Check Off

Report

Objective:                

Create a design that means a performance criteria; pipelining must be used in order to meet the timing requirements.

This lab is worth 50% more than previous labs (150 points instead of 100).

To Do                         TOC  

Modify the blend implementation that you did in Lab #4 so that it will operate at a clock rate of at least 50 Mhz.  Place DFFs on the inputs, and DFFs on the outputs, and use any number of pipeline stages necessary to reach 50 Mhz.  You must use the Flex 10K family, device EPF10K20RC240-4. Use the FAST synthesis option.  If you are using the professional edition, you will use the "show all speed grades" in order to get the "-4" speed grade.  You CANNOT use a speed grade other than "-4".

If you are able to achieve 60 Mhz operation, you will get 5 points added to any test grade.  If you achieve 70 Mhz operation, you will get 10 points added to any test grade. If you achieve 80 Mhz or higher, please get a life (yes, you will get 15 points...).

Call your design "pblend".  Look at the testbench file below to get the port names. It is your "pblend" that must meet the clock rate specification above, NOT the testbench.

Needed Files:                 TOC                            

1. satadd.gdf - saturating adder implementation, uses LPMs.   Use this instead of the VHDL version you did previously.
2. onemalt.gdf -  implements the function "1-F" using LPMs.  Use this instead of the VHDL version you did previously.
3. dff8.vhd, dff9.vhd --   8 and 9 bit registers without an asynchronous reset. You may find these useful or may not.

Testing the Design                     TOC

You can use this schematic (tbpblend.gdf) as the testbench.   This a design problem, which means that there are multiple solutions that will meet the specifications.  I provided  'golden' files that have differring amounts of latency. If anybody needs a golden file with more or less latency that what I have provided below, let me know.

1. lat5gold.scf -- output latency = 5 (testbench)
2. lat6gold.scf -- output latency = 6 (testbench)
3. lat7gold.scf -- output latency = 7 (testbench)
4. lat8gold.scf -- output latency = 8  (testbench)
5. lat9gold.scf --  output latency = 9  (testbench)
6. l10gold.scf -- output latency = 10  (testbench)
7. l11gold.scf -- output latency = 11 (testbench)
8. l12gold.scf -- output latency = 12  (testbench)
9. l13gold.scf -- output latency = 13  (testbench)
10. lat4gold.scf -- output latency = 4 (testbench)
11. lat14gold.scf -- output latency=14 (testbench)
12. lat15gold.scf -- output latency=15 (testbench)

When you are checking your design, particular trouble spots might be where the F value transistions from 0 to a non-zero value or from 1.0 to a value not equal to 1.0.  One cause for failure at these junctures would be if  the amount of latency in paths that bypass the multipler do not equal to the latency within the multiplier.

Check Off                                                                

You must DEMONSTRATE that your design meets the timing specification using speed grade "-4" and also produces the correct output vectors.

Report    

You must hand in plots of all schematics, and report your final maximum frequency.   Hand in a partial plot of the multiplier simulation and show the latency between a set of input values and the correct output value.  EXPLAIN how you modified the original blend implementation to include pipelining.