EE 4743 Test Topics #2 (THIS IS NOT INCLUSIVE!)

You are responsible for anything discussed in class since Test #1. We have concentrated on the following topics:

1. FPGA timing models, calculation of timing paths.
2. FSM design (ASM charts, FSM equations by inspection, FSMs via VHDL, State encoding).
3. Pipelining.
4. Datapath components

I have provide postscript of some old tests. You should be able to work any test question on these sample tests that related to the above topics.

The sample tests have some questions relating to 'flowgraphs' -- we have NOT covered this topic.