Delay Modeling
Simple Gate Delay Models
Variation of t0 and K with Gate size
Simple Transistor Model
Inverter Delay Calculation (TPHL)
Transistor String Delay Calculation
Elmore Delay
Another Transistor String Delay Calculation
From VLSI I: Shared Diffusion Reduces Delay
General RC Tree Delay
Delay Optimization
Transistor Optimization - Full Adder
Carry Logic for Full Adder Cell (Wolf , Prentice Hall)
Move late arriving signals closer to output
Transistor Sizing
TPLH Path
Increasing Successive Stage sizes
Path Delay Optimization
Approaches
TILOS Algorithm (1985, Fishburn & Dunlop)
TILOS Algorithm Comments
Problem….
Path-Oriented Algorithms
Gate Oriented Algorithms (B.Chen ‘98)
Gate Oriented Optimization Approach
Pruning to reduce number of delay paths
Pruning Strategy
Sizing Strategy
Results (B. Chen ‘98)
Parallelism
Email: reese@erc.msstate.edu
Home Page: http://www.erc.msstate.edu/~reese
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