This page contains Frequently Asked Questions about the Mentor QHDL environment.

1. I get the error "** Warning: Time unit 'ps' is less than the simulator resolution." when I run 'qvsim'. What do I do?
   

   The default simulator resolution for 'qvsim' is in nanoseconds (ns). This means that any delays in your simulation will be rounded to the nearest nanosecond. You can edit the 'quickhdl.ini' file and change the 'Resolution' variable to be one of standard VHDL time types (fs, ps, ns, us, ms, sec, min, hr).

2. When I run qvsim it seems to go into an infinite loop; I have to kill it remotely. What is wrong?
   

   This is a VHDL question and not a QHDL question. This is a common problem and usually happens on VHDL processes which do not have a sensitivity list. If a VHDL process does not have a sensitivity list, then it will be continually executed; such a process generally should have a:

       wait;
   

   statement at the end that causes the process to terminate (wait forever). If you leave this out, then the process will simply keep executing forever.

3. When I run 'gmake', I get an error like "*** No rule to make target 'filename'. Stop".

   This is an error in your Makefile and means that you have probably misspelled the name of the VHDL file that is specified as a target within the makefile. The spelling of the file names in the Makefile must match that used in the VHDL source directory.