Problem Statement

Create a Verilog model for a finite state machine that implements a Parallel to Serial Data transmission protocol. The VHDL entity interface is defined as:

   entity  xmit  is 
     generic ( N: integer;  TPERIOD: time)
     port (
           req :           in  std_logic;
           par_data        in std_logic_vector (N-1 downto 0);
           ack :           out   std_logic;
           strobe:         out std_logic;
           data :          out std_logic
             );
   end xmit;

REQ (request) and ACK ( acknowledge) are hand shaking lines for controlling the data transmission. PAR_DATA is the data to be sent in a serial fashion via the STROBE and DATA output lines. PAR_DATA is to be sent serially, least significant bit first (bit 0 is the LSB). Initially, REQ and ACK are '0'. Your entity is to wait until REQ goes from '0' to '1', then it is to send the PAR_DATA serially using the STOBE and DATA output lines. After the last bit is sent, your entity is assert ACK to a '1' and wait for REQ to go a '0'. After REQ goes to a '0', bring the ACK line to a '0', and both DATA and STROBE to a '0' as well. Wait for REQ to go from a '0' to a '1' indicating the start of another transmission. The PAR_DATA is sent over the STROBE/DATA lines in a serial fashion using a method called 'Data Strobe' encoding. An example of data strobe encoding for the value "01110100" is shown below . During one time period (defined by TPERIOD), either STROBE or DATA can change, but not both. STROBE will change if DATA does not change. Note that the DATA and STROBE lines change in the middle of the time period.