--    
--     Simple 4M(8bitX512Kword) DRAM Model for Simulation
--
--     Copyright by S.Takemoto. All rights reserved.
--     Date:12.Jun.1995
--     Permission is granted to freely copy and modify this   
--     software with the copyright notice intact.                   
--     ---------------------------------------------------------
--     Note:
--     
--      This Model was written in order to test circuits in conjunction 
--     with DRAM. It only supports read/write behaivior  and refresh 
--     is not supported(you can read/write without refresh).
--      It returns high-inpeadance when illeagal seaquence occur.
--     (not 'U')
--
--      We tested it on mentor system1076 VHDL simulator with arithmetic
--     library provided by SYNOPSYS. if you do not have SYNOPSY's library,
--     please change fuctions name CONV_*  with similar functions equiped in your
--     simulator.(Of course,it is not synthesizable. :-) )
--     
--     If you hane any questions,plaese contact me.
--  
--     AUther :Satoru Takemoto
--             Fuji Photo Film  Asaka lab.
--             Saitama-Ken Japan
--             TEL  87-48-462-6874
--             E-mail:takemoto@den.fujifilm.co.jp
--     
--
use std.textio.all;
library ieee;
use  ieee.std_logic_1164.all;
use  ieee.std_logic_arith.all;
entity DRAM8 is
  port( A:inout std_logic_vector(9 downto 0);
        D:inout std_logic_vector(7 downto 0):="ZZZZZZZZ";
        RAS,CAS,WE,OE:std_logic
      );
end DRAM8;

architecture memory8 of DRAM8 is
   signal adress:std_logic_vector(9 downto 0);
 
  begin
    RAS_entry:
      process(RAS)
       begin
        if RAS'event and RAS ='0' then
            adress <= A;
        end if;
      end process;

    DAT_IO:
      process(CAS,WE)
        subtype  memory_data is integer range 0 to 255;   --8bit data
        type  memory_array is array ( 0 to 524287) of memory_data;   
        variable int_ad:integer;
        variable adress_all:std_logic_vector(18 downto 0);
        variable DRAM_array: memory_array;
       begin
        if CAS'event and CAS ='0' then
            adress_all:=adress&A(8 downto 0);
        end if;
          int_ad:=CONV_INTEGER(UNSIGNED(adress_all));
         if WE='0' and CAS='0' and RAS='0' then
              DRAM_array(int_ad):=CONV_INTEGER(UNSIGNED(D));
         elsif
            WE='1' and  CAS='0'  and RAS='0' then
              D <=STD_LOGIC_VECTOR(CONV_UNSIGNED( DRAM_array(int_ad),8));
         elsif
          CAS'event and CAS='1' then
             D <= "ZZZZZZZZ" after 20 ns;
         end if;
       end process;
end  memory8;