----------------------------------------------------------------------------
--
--	(c) COPYRIGHT 1989 ZYCAD CORPORATION.  
-- 	This source file may be used and distributed without restriction 
--	provided that the copyright is not removed and that the code is 
--	not used or distributed for profit.
--
--	Package name: COMPONENTS
--
--	Purpose: A set of primitives for Zycad's Standard Logic library.
--
--	Author: JT, PH, GWH
--
--	NOTE: The types used by this package are defined in the package
--	      ZYCAD.TYPES
--	      The models (entity/architecture pairs) for these primitives
--	      are defined in the package ZYCAD.ENTITIES
--
----------------------------------------------------------------------------
library ZYCAD;
use ZYCAD.TYPES.all;

package COMPONENTS is

    ------------------------------------------------------------------------
    --
    -- Logic gates for n inputs
    --
    ------------------------------------------------------------------------

    component ANDGATE				-- N input AND gate
	generic (N:   Positive := 2;		-- number of inputs
		 tLH: Time := 0 ns;		-- rise inertial delay
		 tHL: Time := 0 ns);		-- fall inertial delay
	port (Input: in MVL4_VECTOR (1 to N);	-- input
	      Output: out MVL4);		-- output
    end component;

    component NANDGATE				-- N input NAND gate
	generic (N:   Positive := 2;		-- number of inputs
		 tLH: Time := 0 ns;		-- rise inertial delay
		 tHL: Time := 0 ns);		-- fall inertial delay
	port (Input: in MVL4_VECTOR (1 to N);	-- input
	      Output: out MVL4);		-- output
    end component;

    component ORGATE				-- N input OR gate
	generic (N:   Positive := 2;		-- number of inputs
		 tLH: Time := 0 ns;		-- rise inertial delay
		 tHL: Time := 0 ns);		-- fall inertial delay
	port (Input: in MVL4_VECTOR (1 to N);	-- input
	      Output: out MVL4);		-- output
    end component;

    component NORGATE				-- N input NOR gate
	generic (N:   Positive := 2;		-- number of inputs
		 tLH: Time := 0 ns;		-- rise inertial delay
		 tHL: Time := 0 ns);		-- fall inertial delay
	port (Input: in MVL4_VECTOR (1 to N);	-- input
	      Output: out MVL4);		-- output
    end component;

    component XORGATE				-- N input XOR gate
	generic (N:   Positive := 2;		-- number of inputs
		 tLH: Time := 0 ns;		-- rise inertial delay
		 tHL: Time := 0 ns);		-- fall inertial delay
	port (Input: in MVL4_VECTOR (1 to N);	-- input
	      Output: out MVL4);		-- output
    end component;

    component NXORGATE				-- N input NXOR gate
	generic (N:   Positive := 2;		-- number of inputs
		 tLH: Time := 0 ns;		-- rise inertial delay
		 tHL: Time := 0 ns);		-- fall inertial delay
	port (Input: in MVL4_VECTOR (1 to N);	-- input
	      Output: out MVL4);		-- output
    end component;


    --------------------------------------------------------------------------
    --
    -- Transfer gates 
    --
    -------------------------------------------------------------------------
    component BUFGATE				-- buffer
	generic (tLH: Time := 0 ns;		-- rise inertial delay
		 tHL: Time := 0 ns);		-- fall inertial delay
	port (Input: in MVL4;			-- input
	      Output: out MVL4);		-- output
    end component;

    component INVGATE				-- inverter
	generic (tLH: Time := 0 ns;		-- rise inertial delay
		 tHL: Time := 0 ns);		-- fall inertial delay
	port (Input: in MVL4;			-- input
	      Output: out MVL4);		-- output
    end component;


    --------------------------------------------------------------------------
    --
    -- Tristate transfer gates 
    --
    -------------------------------------------------------------------------
    component BUF3S				-- tristate buffer
	generic (tLH: Time := 0 ns;		-- rise inertial delay
		 tHL: Time := 0 ns);		-- fall inertial delay

	port (Input: in MVL4;			-- input
	      Enable: in MVL4;			-- enable
	      Output: out MVL4);		-- output
    end component;

    component INV3S				-- tristate inverter
	generic (tLH: Time := 0 ns;		-- rise inertial delay
		 tHL: Time := 0 ns);		-- fall inertial delay
	port (Input: in MVL4;			-- input
	      Enable: in MVL4;			-- enable
	      Output: out MVL4);		-- output
    end component;

    --------------------------------------------------------------------------
    --
    -- Other logic primitives
    --
    --------------------------------------------------------------------------

    component KEEPER				-- bus keeper
	generic (tLH: Time := 0 ns;		-- rise inertial delay
		 tHL: Time := 0 ns);		-- fall inertial delay
	port (Input: in MVL4;			-- input
	      Output: out MVL4);		-- output
    end component;

    component MAJORITY				-- majority gate
	generic (tLH: Time :=  0 ns;		-- rise inertial delay
		 tHL: Time :=  0 ns);		-- fall inertial delay
	port (In1, In2, In3: in MVL4;		-- inputs
	      Output: out MVL4);		-- output
    end component;

    component MUX2x1				-- 2 by 1 multiplexer
	generic (tLH: Time :=  0 ns;		-- rise inertial delay
		 tHL: Time :=  0 ns);		-- fall inertial delay
	port (In0,				-- data input 0
	      In1,				-- data input 1
	      Sel: in MVL4;			-- select input (0=>In0)
	      Output: out MVL4);		-- output
    end component;


    -------------------------------------------------------------------------
    --
    -- State primitives
    --
    -------------------------------------------------------------------------
    component DFF				-- D flip flop
	generic (tLH: Time :=  0 ns;		-- rise inertial delay
		 tHL: Time :=  0 ns);		-- fall inertial delay
	port (Data,				-- data input 
	      Clock,				-- clock input
	      Reset: in MVL4;			-- reset input
	      Output: out MVL4);		-- output 
    end component;

    component DLATCH				-- D latch
	generic (tLH: Time :=  0 ns;		-- rise inertial delay
		 tHL: Time :=  0 ns);		-- fall inertial delay
	port (Data,				-- data input 
	      Enable,				-- enable input
	      Reset: in MVL4;			-- reset input 
	      Output: out MVL4);		-- output 
    end component;

    component REG_EDGE
	generic (N: Positive :=1;			-- N bit edge register
		 tLH: Time :=  0 ns;			-- rise inertial delay
		 tHL: Time :=  0 ns);			-- fall inertial delay
	port (Data: in MVL4_VECTOR (N-1 downto 0);	-- data input
	      Clock,					-- clock input
	      Reset: in MVL4;				-- reset input
	      Output: out MVL4_VECTOR (N-1 downto 0));	-- output
    end component;

    component REG_LEVEL
	generic (N: Positive :=1;			-- N bit level register
		 tLH: Time :=  0 ns;			-- rise inertial delay
		 tHL: Time :=  0 ns);			-- fall inertial delay
	port (Data: in MVL4_VECTOR (N-1 downto 0);	-- data input
	      Enable,					-- enable input
	      Reset: in MVL4;				-- reset input
	      Output: out MVL4_VECTOR (N-1 downto 0));	-- output
    end component;

    
    ---------------------------------------------------------------------------
    --
    -- Memory primitives
    --
    ---------------------------------------------------------------------------
    component RAM_EDGE
	generic (Ndata: Positive;			-- # of data lines
		 Naddr: Positive;			-- # of address lines
		 UndefFlag: Boolean :=  FALSE);		-- TRUE => undef.val.ok
	port (DATAin: in MVL4_VECTOR (Ndata-1 downto 0); -- data in lines
	      DATAout: out MVL4_VECTOR (Ndata-1 downto 0); -- data out lines
	      ADDR: in MVL4_VECTOR (Naddr-1 downto 0);	-- address lines
	      INIT,					-- initial control line
	      W,					-- write control line
	      R: in MVL4;				-- read control line
	      ERR: out MVL4);				-- error flag
    end component;

    component RAM_LEVEL
	    generic (Ndata: Positive;			-- # of data lines
		     Naddr: Positive);			-- # of address lines
	    port (DATAin: in MVL4_VECTOR(Ndata-1 downto 0); -- data in lines
		  DATAout: out MVL4_VECTOR(Ndata-1 downto 0); -- data out lines
		  ADDR: in MVL4_VECTOR(Naddr-1 downto 0); -- address lines
		  CE: in MVL4;				-- chip enable
		  RW: in MVL4);				-- read(active low) and
							-- write(active high)
    end component;


    ------------------------------------------------------------------------
    --
    -- Logic gates for 2, 3, and 4 inputs
    --
    ------------------------------------------------------------------------
    component AND2				-- 2 input AND gate
	generic (tLH: Time := 0 ns;		-- rise inertial delay
		 tHL: Time := 0 ns);		-- fall inertial delay
	port (In1, In2: in MVL4;		-- inputs
	      Output: out MVL4);		-- output
    end component;

    component AND3				-- 3 input AND gate
	generic (tLH: Time := 0 ns;		-- rise inertial delay
		 tHL: Time := 0 ns);		-- fall inertial delay
	port (In1, In2, In3: in MVL4;		-- inputs
	      Output: out MVL4);		-- output
    end component;

    component AND4				-- 4 input AND gate
	generic (tLH: Time := 0 ns;		-- rise inertial delay
		 tHL: Time := 0 ns);		-- fall inertial delay
	port (In1, In2, In3, In4: in MVL4;	-- inputs
	      Output: out MVL4);		-- output
    end component;

    component NAND2				-- 2 input NAND gate
	generic (tLH: Time := 0 ns;		-- rise inertial delay
		 tHL: Time := 0 ns);		-- fall inertial delay
	port (In1, In2: in MVL4;		-- inputs
	      Output: out MVL4);		-- output
    end component;

    component NAND3				-- 3 input NAND gate
	generic (tLH: Time := 0 ns;		-- rise inertial delay
		 tHL: Time := 0 ns);		-- fall inertial delay
	port (In1, In2, In3: in MVL4;		-- inputs
	      Output: out MVL4);		-- output
    end component;

    component NAND4				-- 4 input NAND gate
	generic (tLH: Time := 0 ns;		-- rise inertial delay
		 tHL: Time := 0 ns);		-- fall inertial delay
	port (In1, In2, In3, In4: in MVL4;	-- inputs
	      Output: out MVL4);		-- output
    end component;


    component OR2				-- 2 input OR gate
	generic (tLH: Time := 0 ns;		-- rise inertial delay
		 tHL: Time := 0 ns);		-- fall inertial delay
	port (In1, In2: in MVL4;		-- inputs
	      Output: out MVL4);		-- output
    end component;

    component OR3				-- 3 input OR gate
	generic (tLH: Time := 0 ns;		-- rise inertial delay
		 tHL: Time := 0 ns);		-- fall inertial delay
	port (In1, In2, In3: in MVL4;		-- inputs
	      Output: out MVL4);		-- output
    end component;

    component OR4				-- 4 input OR gate
	generic (tLH: Time := 0 ns;		-- rise inertial delay
		 tHL: Time := 0 ns);		-- fall inertial delay
	port (In1, In2, In3, In4: in MVL4;	-- inputs
	      Output: out MVL4);		-- output
    end component;


    component NOR2				-- 2 input NOR gate
	generic (tLH: Time := 0 ns;		-- rise inertial delay
		 tHL: Time := 0 ns);		-- fall inertial delay
	port (In1, In2: in MVL4;		-- inputs
	      Output: out MVL4);		-- output
    end component;

    component NOR3				-- 3 input NOR gate
	generic (tLH: Time := 0 ns;		-- rise inertial delay
		 tHL: Time := 0 ns);		-- fall inertial delay
	port (In1, In2, In3: in MVL4;		-- inputs
	      Output: out MVL4);		-- output
    end component;

    component NOR4				-- 4 input NOR gate
	generic (tLH: Time := 0 ns;		-- rise inertial delay
		 tHL: Time := 0 ns);		-- fall inertial delay
	port (In1, In2, In3, In4: in MVL4;	-- inputs
	      Output: out MVL4);		-- output
    end component;


    component XOR2				-- 2 input XOR gate
	generic (tLH: Time := 0 ns;		-- rise inertial delay
		 tHL: Time := 0 ns);		-- fall inertial delay
	port (In1, In2: in MVL4;		-- inputs
	      Output: out MVL4);		-- output
    end component;

    component XOR3				-- 3 input XOR gate
	generic (tLH: Time := 0 ns;		-- rise inertial delay
		 tHL: Time := 0 ns);		-- fall inertial delay
	port (In1, In2, In3: in MVL4;		-- inputs
	      Output: out MVL4);		-- output
    end component;

    component XOR4				-- 4 input XOR gate
	generic (tLH: Time := 0 ns;		-- rise inertial delay
		 tHL: Time := 0 ns);		-- fall inertial delay
	port (In1, In2, In3, In4: in MVL4;	-- inputs
	      Output: out MVL4);		-- output
    end component;


    component NXOR2				-- 2 input NXOR gate
	generic (tLH: Time := 0 ns;		-- rise inertial delay
		 tHL: Time := 0 ns);		-- fall inertial delay
	port (In1, In2: in MVL4;		-- inputs
	      Output: out MVL4);		-- output
    end component;

    component NXOR3				-- 3 input NXOR gate
	generic (tLH: Time := 0 ns;		-- rise inertial delay
		 tHL: Time := 0 ns);		-- fall inertial delay
	port (In1, In2, In3: in MVL4;		-- inputs
	      Output: out MVL4);		-- output
    end component;

    component NXOR4				-- 4 input NXOR gate
	generic (tLH: Time := 0 ns;		-- rise inertial delay
		 tHL: Time := 0 ns);		-- fall inertial delay
	port (In1, In2, In3, In4: in MVL4;	-- inputs
	      Output: out MVL4);		-- output
    end component;


end COMPONENTS;