package BASICDEFS is
-----------------------------------------------------------------------
--
--   The following is a preliminary definition of the basic logic system 
--   and associated operators/functions used for the EIA VHDL Model 
--   Commercial Component Specification.
--
--   Created by Dave Cantwell/Hughes  (714-670-4677)
--            & Len Finegold/General Dynamics 
--
--   COPYRIGHT C Hughes Aircraft Co. 1989
--   Created 1/25/90
--   Version 0.1
-----------------------------------------------------------------------
---
   TYPE logic_mv is ('U', 'X', '0', '1', 'Z', 'L', 'H'); 
   TYPE logic_vector_mv is array (natural range <>) of logic_mv;
   TYPE logic_mv_table is array (logic_mv, logic_mv) of logic_mv;
---                                                         
-- Logic conversion functions
---
------------------------------------------------------------------------
-- SCALAR FUNCTIONS
------------------------------------------------------------------------
-- OVERLOADED OPERATORS
--                               
FUNCTION "and"  ( i1,i2 : logic_mv )	RETURN logic_mv ;
FUNCTION "nand" ( i1,i2 : logic_mv )	RETURN logic_mv ;
FUNCTION "or"   ( i1,i2 : logic_mv )	RETURN logic_mv ;
FUNCTION "nor"  ( i1,i2 : logic_mv )	RETURN logic_mv ;
FUNCTION "xor"  ( i1,i2 : logic_mv )	RETURN logic_mv ;
FUNCTION "not"  ( i1    : logic_mv )	RETURN logic_mv ;
-- NOT A PREDEFINED OPERATOR, THUS IS NOT OVERLOADED.
FUNCTION  xnor   ( i1,i2 : logic_mv )	RETURN logic_mv ;
--
------------------------------------------------------------------------
-- VECTORIZED FUNCTIONS
------------------------------------------------------------------------
--
FUNCTION "and"  ( i1,i2 : logic_vector_mv )	RETURN logic_vector_mv ;
FUNCTION "nand" ( i1,i2 : logic_vector_mv )	RETURN logic_vector_mv ;
FUNCTION "or"   ( i1,i2 : logic_vector_mv )	RETURN logic_vector_mv ;
FUNCTION "nor"  ( i1,i2 : logic_vector_mv )	RETURN logic_vector_mv ;
FUNCTION "xor"  ( i1,i2 : logic_vector_mv )	RETURN logic_vector_mv ;
FUNCTION "not"  ( i1    : logic_vector_mv )	RETURN logic_vector_mv ;
-- NOT A PREDEFINED OPERATOR, THUS IS NOT OVERLOADED.
FUNCTION xnor ( i1,i2 : logic_vector_mv )	RETURN logic_vector_mv ;
--
-- BIT-WISE REDUCTION FUNCTIONS
--                               
FUNCTION and_bw  ( i1 :  logic_vector_mv )	RETURN logic_mv;
FUNCTION nand_bw ( i1 :  logic_vector_mv )	RETURN logic_mv;
FUNCTION or_bw   ( i1 :  logic_vector_mv )	RETURN logic_mv;
FUNCTION nor_bw  ( i1 :  logic_vector_mv )	RETURN logic_mv;
FUNCTION xor_bw  ( i1 :  logic_vector_mv )	RETURN logic_mv;
FUNCTION xnor_bw ( i1 :  logic_vector_mv )	RETURN logic_mv;
--
------------------------------------------------------------------------
--  Comparison Operators
------------------------------------------------------------------------
FUNCTION "="  (i1, i2: logic_mv) 		RETURN logic_mv ;
FUNCTION "/=" (i1, i2: logic_mv) 		RETURN logic_mv ;
FUNCTION "="  (i1,i2 : logic_vector_mv )	RETURN logic_mv ;
FUNCTION "/=" (i1,i2 : logic_vector_mv )	RETURN logic_mv ;
--
------------------------------------------------------------------------
---   Bus Resolution Functions
------------------------------------------------------------------------
-- The following function shall be used for standard components
FUNCTION Wired_Outputs (signals : logic_vector_mv) RETURN logic_mv ;
-- The following functions shall be used for on chip development ONLY
FUNCTION Wired_Or  (signals : logic_vector_mv) RETURN logic_mv ;
FUNCTION Wired_And (signals : logic_vector_mv) RETURN logic_mv ;
--
-----------------------------------------------------------------------
--  Miscellaneous Function(s)
-----------------------------------------------------------------------
--  Function to translate H, L, or Z on inputs to 1, 0 or X respectively.
--  Example usage:  In a RAM model, without this function, a HIGH or LOW
--  state would be stored internally from the bus and subsequently be 
--  erroneously driven onto the bus during a read operation.  
FUNCTION Filter (input : logic_mv) RETURN logic_mv ;
--
-----------------------------------------------------------------------
--  Signal transitions and relationships
-----------------------------------------------------------------------
--
FUNCTION Posedge( signal s1 : logic_mv)  RETURN boolean ;
FUNCTION Negedge( signal s1 : logic_mv)  RETURN boolean ;   
-- Posedge and Negedge functions return TRUE on 0->1 or 1->0 transitions only
--
PROCEDURE Setup_check (constant input_le : time; constant time_spec : time; 
                constant message : string; constant err_level : severity_level);

PROCEDURE Hold_check (constant input_le : time; constant time_spec : time; 
                constant message : string; constant err_level : severity_level);
--
-- The following illustrates how to imbed setup and hold checks procedures
-- into the vhdl models
--
-- DATA_CLOCK_SETUP: process 
-- begin
--   wait on clk until do_timing_checks and posedge(clk,clk'last_value);
--   Setup_check (data'last_event, model_times.ts_data, "DATA to CLOCK", 
--                warning);
-- end process DATA_CLOCK_SETUP;
--
-- DATA_CLOCK_HOLD: process 
-- begin
--   wait on clk until do_timing_checks and posedge(clk,clk'last_value);
--   wait for th_data;
--   Hold_check (data'last_event, model_times.th_data, "DATA to CLOCK", 
--               warning);
-- end process DATA_CLOCK_HOLD;
--
------------------------------------------------------------------------------
--
--   function name: F_delay
--   parameters:  
--       in         newlv   --  bit_mv    -- new logic value
--       in         delay01 --  time      -- 0->1 delay value
--       in         delay10 --  time      -- 1->0 delay value
-- 
--   returns:       The appropriate delay to be used, given the new value
--                  and the 0-1 and 1-0 delays.
--
--   purpose:       Compute the appropriate delay to be used for a transition
--                  on an output port.
--
------------------------------------------------------------------------------
    
  FUNCTION F_delay(newlv : IN logic_mv; delay01 : IN time; delay10 : IN time) 
           RETURN time;

end BASICDEFS;
------------------------------------------------------------------------------
------------------------------------------------------------------------------
------------------------------------------------------------------------------
------------------------------------------------------------------------------
package body BASICDEFS is
-----------------------------------------------------------------------
--
--   The following is a preliminary definition of the basic logic system 
--   and associated operators/functions used for the EIA VHDL Model 
--   Commercial Component Specification.
--
--   Created by Dave Cantwell/Hughes  (714-670-4677)
--            & Len Finegold/General Dynamics 
--
--   COPYRIGHT C Hughes Aircraft Co. 1989
--   Created 1/25/90
--   Version 0.1
------------------------------------------------------------------------
-- CONSTANT DECLARATIONS FOR USE IN SIGNAL & VARIABLE ASSIGNMENTS
------------------------------------------------------------------------
   constant MAX_SIZE : POSITIVE := 32;  -- This is a deferred constant 
    		  -- which should be initialized to the largest size bus 
                  -- in design

   constant UNINITIALIZED : logic_mv := 'U';
   constant UNKNOWN       : logic_mv := 'X';
   constant ZERO          : logic_mv := '0';
   constant ONE           : logic_mv := '1';
   constant HIGHZ         : logic_mv := 'Z';
   constant LOW           : logic_mv := 'L';
   constant HIGH          : logic_mv := 'H';

   constant ALL_UNINITIALIZED  : logic_vector_mv(MAX_SIZE-1 DOWNTO 0) 
				:= (others => UNINITIALIZED);
   constant ALL_UNKNOWN       : logic_vector_mv(MAX_SIZE-1 DOWNTO 0) 
				:= (others => UNKNOWN);
   constant ALL_ZERO          : logic_vector_mv(MAX_SIZE-1 DOWNTO 0) 
				:= (others => ZERO);
   constant ALL_ONE           : logic_vector_mv(MAX_SIZE-1 DOWNTO 0) 
				:= (others => ONE);
   constant ALL_HIGHZ         : logic_vector_mv(MAX_SIZE-1 DOWNTO 0)
				:= (others => HIGHZ);
   constant ALL_LOW           : logic_vector_mv(MAX_SIZE-1 DOWNTO 0) 
				:= (others => LOW);
   constant ALL_HIGH          : logic_vector_mv(MAX_SIZE-1 DOWNTO 0)
				:= (others => HIGH);
--
------------------------------------------------------------------------
-- TYPE DECLARATIONS FOR USE IN SUBPROGRAM BODIES
------------------------------------------------------------------------
--
   type logic_mv_array is array (logic_mv) of logic_mv;
--
------------------------------------------------------------------------
-- SCALAR FUNCTIONS
------------------------------------------------------------------------
--
FUNCTION "and" ( i1,i2 :  logic_mv )	RETURN logic_mv is

   constant Table  : logic_mv_table :=
      ((UNKNOWN, UNKNOWN, ZERO, UNKNOWN, UNKNOWN, ZERO, UNKNOWN),
       (UNKNOWN, UNKNOWN, ZERO, UNKNOWN, UNKNOWN, ZERO, UNKNOWN),
       (ZERO,    ZERO,    ZERO, ZERO,    ZERO,    ZERO, ZERO),
       (UNKNOWN, UNKNOWN, ZERO, ONE,     UNKNOWN, ZERO, ONE),
       (UNKNOWN, UNKNOWN, ZERO, UNKNOWN, UNKNOWN, ZERO, UNKNOWN),
       (ZERO,    ZERO,    ZERO, ZERO,    ZERO,    ZERO, ZERO),
       (UNKNOWN, UNKNOWN, ZERO, ONE,     UNKNOWN, ZERO, ONE));

BEGIN
   
RETURN Table(i1, i2);

END "and";
------------------------------------------------------------------------

FUNCTION "nand" ( i1,i2 :  logic_mv )	RETURN logic_mv is

   constant Table  : logic_mv_table :=
      ((UNKNOWN, UNKNOWN, ONE, UNKNOWN, UNKNOWN, ONE, UNKNOWN),
       (UNKNOWN, UNKNOWN, ONE, UNKNOWN, UNKNOWN, ONE, UNKNOWN),
       (ONE,     ONE,     ONE, ONE,     ONE,     ONE, ONE),
       (UNKNOWN, UNKNOWN, ONE, ZERO,    UNKNOWN, ONE, ZERO),
       (UNKNOWN, UNKNOWN, ONE, UNKNOWN, UNKNOWN, ONE, UNKNOWN),
       (ONE,     ONE,     ONE, ONE,     ONE,     ONE, ONE),
       (UNKNOWN, UNKNOWN, ONE, ZERO,    UNKNOWN, ONE, ZERO));
BEGIN
   
RETURN Table(i1, i2);

END "nand";
------------------------------------------------------------------------

FUNCTION "or" ( i1,i2 :  logic_mv )	RETURN logic_mv is

   constant Table  : logic_mv_table :=
      ((UNKNOWN, UNKNOWN, UNKNOWN, ONE, UNKNOWN, UNKNOWN, ONE),
       (UNKNOWN, UNKNOWN, UNKNOWN, ONE, UNKNOWN, UNKNOWN, ONE),
       (UNKNOWN, UNKNOWN, ZERO,    ONE, UNKNOWN, ZERO,    ONE),
       (ONE,     ONE,     ONE,     ONE, ONE,     ONE,     ONE),
       (UNKNOWN, UNKNOWN, UNKNOWN, ONE, UNKNOWN, UNKNOWN, ONE),
       (UNKNOWN, UNKNOWN, ZERO,    ONE, UNKNOWN, ZERO,    ONE),
       (ONE,     ONE,     ONE,     ONE, ONE,     ONE,     ONE));
BEGIN
   
RETURN Table(i1, i2);

END "or";
------------------------------------------------------------------------

FUNCTION "nor" ( i1,i2 :  logic_mv )	RETURN logic_mv is

   constant Table  : logic_mv_table :=
      ((UNKNOWN, UNKNOWN, UNKNOWN, ZERO, UNKNOWN, UNKNOWN, ZERO),
       (UNKNOWN, UNKNOWN, UNKNOWN, ZERO, UNKNOWN, UNKNOWN, ZERO),
       (UNKNOWN, UNKNOWN, ONE,     ZERO, UNKNOWN, ONE,     ZERO),
       (ZERO,    ZERO,    ZERO,    ZERO, ZERO,    ZERO,    ZERO),
       (UNKNOWN, UNKNOWN, UNKNOWN, ZERO, UNKNOWN, UNKNOWN, ZERO),
       (UNKNOWN, UNKNOWN, ONE,     ZERO, UNKNOWN, ONE,     ZERO),
       (ZERO,    ZERO,    ZERO,    ZERO, ZERO,    ZERO,    ZERO));
BEGIN
   
RETURN Table(i1, i2);

END "nor";
------------------------------------------------------------------------

FUNCTION "xor" ( i1,i2 :  logic_mv )	RETURN logic_mv is

   constant Table  : logic_mv_table :=
      ((UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN),
       (UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN),
       (UNKNOWN, UNKNOWN, ZERO,    ONE,     UNKNOWN, ZERO,    ONE),
       (UNKNOWN, UNKNOWN, ONE,     ZERO,    UNKNOWN, ONE,     ZERO),
       (UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN),
       (UNKNOWN, UNKNOWN, ZERO,    ONE,     UNKNOWN, ZERO,    ONE),
       (UNKNOWN, UNKNOWN, ONE,     ZERO,    UNKNOWN, ONE,     ZERO));
BEGIN
   
RETURN Table(i1, i2);

END "xor";
------------------------------------------------------------------------

FUNCTION xnor ( i1,i2 :  logic_mv )	RETURN logic_mv is

   constant Table  : logic_mv_table :=
      ((UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN),
       (UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN),
       (UNKNOWN, UNKNOWN, ONE,     ZERO,    UNKNOWN, ONE,     ZERO),
       (UNKNOWN, UNKNOWN, ZERO,    ONE,     UNKNOWN, ZERO,    ONE),
       (UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN),
       (UNKNOWN, UNKNOWN, ONE,     ZERO,    UNKNOWN, ONE,     ZERO),
       (UNKNOWN, UNKNOWN, ZERO,    ONE,     UNKNOWN, ZERO,    ONE));
BEGIN
   
RETURN Table(i1, i2);

END xnor;
------------------------------------------------------------------------

FUNCTION "not" ( i1 :  logic_mv )	RETURN logic_mv is

   constant Table  : logic_mv_array :=
      (UNKNOWN, UNKNOWN, ONE, ZERO, UNKNOWN, ONE, ZERO);
BEGIN
   
RETURN Table(i1);
END "not";
--
------------------------------------------------------------------------
-- VECTORIZED FUNCTIONS
------------------------------------------------------------------------
--
FUNCTION "and" ( i1,i2 :  logic_vector_mv )	RETURN logic_vector_mv is

    alias Arg1 : logic_vector_mv (1 to i1'length) is i1;
    alias Arg2 : logic_vector_mv (1 to i2'length) is i2;
    variable Store : logic_vector_mv (1 to i1'length );

BEGIN
    assert i1'length = i2'length report "Bus width mismatch" severity warning;
    FOR i in Store'range LOOP
        Store(i) := Arg1(i) and Arg2(i);
    END LOOP;
RETURN Store;
END "and";
------------------------------------------------------------------------

FUNCTION "nand" ( i1,i2 :  logic_vector_mv )	RETURN logic_vector_mv is

    alias Arg1 : logic_vector_mv (1 to i1'length) is i1;
    alias Arg2 : logic_vector_mv (1 to i2'length) is i2;
    variable Store : logic_vector_mv( 1 to i1'length);               

BEGIN
    assert i1'length = i2'length report "Bus width mismatch" severity warning;
    FOR i in Store'range LOOP
        Store(i) := Arg1(i) nand Arg2(i);
    END LOOP;
RETURN Store;
END "nand";                              
------------------------------------------------------------------------

FUNCTION "or" ( i1,i2 :  logic_vector_mv )	RETURN logic_vector_mv is

    alias Arg1 : logic_vector_mv (1 to i1'length) is i1;
    alias Arg2 : logic_vector_mv (1 to i2'length) is i2;
    variable Store : logic_vector_mv( 1 to i1'length);

BEGIN
    assert i1'length = i2'length report "Bus width mismatch" severity warning;
    FOR i in Store'range LOOP
        Store(i) := Arg1(i) or Arg2(i);
    END LOOP;
RETURN Store;
END "or";
------------------------------------------------------------------------

FUNCTION "nor" ( i1,i2 :  logic_vector_mv )	RETURN logic_vector_mv is

    alias Arg1 : logic_vector_mv (1 to i1'length) is i1;
    alias Arg2 : logic_vector_mv (1 to i2'length) is i2;
    variable Store : logic_vector_mv( 1 to i1'length );

BEGIN
    assert i1'length = i2'length report "Bus width mismatch" severity warning;
    FOR i in Store'range LOOP
          Store(i) := Arg1(i) nor Arg2(i);
    END LOOP;
RETURN Store;
END "nor";
------------------------------------------------------------------------

FUNCTION "xor" ( i1,i2 :  logic_vector_mv )	RETURN logic_vector_mv is

    alias Arg1 : logic_vector_mv (1 to i1'length) is i1;
    alias Arg2 : logic_vector_mv (1 to i2'length) is i2;
    variable Store : logic_vector_mv( 1 to i1'length );

BEGIN
    assert i1'length = i2'length report "Bus width mismatch" severity warning;
    FOR i in Store'range LOOP
        Store(i) := Arg1(i) xor Arg2(i);
    END LOOP;
RETURN Store;
END "xor";
------------------------------------------------------------------------

FUNCTION xnor ( i1,i2 :  logic_vector_mv )	RETURN logic_vector_mv is

    alias Arg1 : logic_vector_mv (1 to i1'length) is i1;
    alias Arg2 : logic_vector_mv (1 to i2'length) is i2;
    variable Store : logic_vector_mv( 1 to i1'length );

BEGIN
    assert i1'length = i2'length report "Bus width mismatch" severity warning;
    FOR i in Store'range LOOP
        Store(i) := xnor ( Arg1(i), Arg2(i) );
    END LOOP;
RETURN Store;
END xnor;
------------------------------------------------------------------------

FUNCTION "not" ( i1 :  logic_vector_mv )	RETURN logic_vector_mv is

    variable Store : logic_vector_mv( i1'range);

BEGIN
    FOR i in Store'range LOOP
        Store(i) := not i1(i);
    END LOOP;
RETURN Store;
END "not";
--
------------------------------------------------------------------------
-- BIT-WISE REDUCTION OPERATORS
------------------------------------------------------------------------
-- 
FUNCTION and_bw ( i1 :  logic_vector_mv )		RETURN logic_mv is

    variable Store : logic_mv := i1(i1'low);

BEGIN   
--    IF i1'length > 1 then
        FOR i in i1'low+1 to i1'high LOOP
            CASE Store is 
              when ZERO|LOW =>  RETURN ZERO;
              when ONE|HIGH =>  CASE i1(i) is
                                 when ZERO|LOW   =>  RETURN ZERO;
                                 when ONE|HIGH   =>  NULL;
                                 when others    =>  Store := UNKNOWN;
                               END CASE;
              when others  =>  CASE i1(i) is
                                 when ZERO|LOW   =>  RETURN ZERO;
                                 when others    =>  Store := UNKNOWN;
                               END CASE;
            END CASE;
        END LOOP;
--    END IF;
RETURN Filter(Store); 
END and_bw;
------------------------------------------------------------------------

FUNCTION nand_bw ( i1 :  logic_vector_mv )		RETURN logic_mv is

    variable Store : logic_mv := i1(i1'low);

BEGIN   
--    IF i1'length > 1 then
        FOR i in i1'low+1 to i1'high LOOP
            CASE Store is 
              when ZERO|LOW =>  RETURN ONE;
              when ONE|HIGH =>  CASE i1(i) is
                                 when ZERO|LOW   =>  RETURN ONE;
                                 when ONE|HIGH   =>  NULL;
                                 when others    =>  Store := UNKNOWN;
                               END CASE;
              when others  =>  CASE i1(i) is
                                 when ZERO|LOW   =>  RETURN ONE;
                                 when others    =>  Store := UNKNOWN;
                               END CASE;
            END CASE;
        END LOOP;
--    END IF;
RETURN not Store;
END nand_bw;
------------------------------------------------------------------------

FUNCTION or_bw ( i1 :  logic_vector_mv )		RETURN logic_mv is

    variable Store : logic_mv := i1(i1'low);

BEGIN   
--    IF i1'length > 1 then
        FOR i in i1'low+1 to i1'high LOOP
            CASE Store is 
              when ONE|HIGH =>  RETURN ONE;
              when ZERO|LOW =>  CASE i1(i) is
                                 when ZERO|LOW   =>  NULL;
                                 when ONE|HIGH   =>  RETURN ONE;
                                 when others    =>  Store := UNKNOWN;
                               END CASE;
              when others  =>  CASE i1(i) is
                                 when ONE|HIGH   =>  RETURN ONE;
                                 when others    =>  Store := UNKNOWN;
                               END CASE;
            END CASE;
        END LOOP;
--    END IF;
RETURN Filter(Store);
END or_bw;
------------------------------------------------------------------------

FUNCTION nor_bw ( i1 :  logic_vector_mv )		RETURN logic_mv is

    variable Store : logic_mv := i1(i1'low);

BEGIN   
--    IF i1'length > 1 then
        FOR i in i1'low+1 to i1'high LOOP
            CASE Store is 
              when ONE|HIGH =>  RETURN ZERO;
              when ZERO|LOW =>  CASE i1(i) is
                                 when ZERO|LOW   =>  NULL;
                                 when ONE|HIGH   =>  RETURN ZERO;
                                 when others    =>  Store := UNKNOWN;
                               END CASE;
              when others  =>  CASE i1(i) is
                                 when ONE|HIGH   =>  RETURN ZERO;
                                 when others    =>  Store := UNKNOWN;
                               END CASE;
            END CASE;
        END LOOP;
--    END IF;
RETURN not Store;
END nor_bw;
------------------------------------------------------------------------

FUNCTION xor_bw ( i1 : logic_vector_mv )	RETURN logic_mv is

    variable Store : logic_mv := i1(i1'low);

BEGIN
   IF i1'length > 1 then
       FOR i in i1'low+1 TO i1'high LOOP
           CASE Store is
               when ZERO|LOW => CASE i1(i) IS
                                 when ZERO|LOW    =>  NULL;
                                 when ONE|HIGH    =>  RETURN ONE;
                                 when others =>  RETURN UNKNOWN;
                               END CASE;
               when ONE|HIGH => CASE i1(i) IS
                                 when ZERO|LOW    =>  RETURN ONE;
                                 when ONE|HIGH    =>  NULL;
                                 when others =>  RETURN UNKNOWN;
                               END CASE;
               when others =>  RETURN UNKNOWN;
            END CASE;
        END LOOP;
        RETURN ZERO;
    else
        RETURN Filter(Store);
    END IF;
END xor_bw;
------------------------------------------------------------------------

FUNCTION xnor_bw ( i1 : logic_vector_mv )	RETURN logic_mv is

    variable Store : logic_mv := i1(i1'low);

BEGIN
   IF i1'length > 1 then
        FOR i in i1'low+1 TO i1'high LOOP
           CASE Store is
               when ZERO|LOW => CASE i1(i) IS
                                 when ZERO|LOW    =>  NULL;
                                 when ONE|HIGH    =>  RETURN ZERO;
                                 when others =>  RETURN UNKNOWN;
                               END CASE;
               when ONE|HIGH => CASE i1(i) IS
                                 when ZERO|LOW    =>  RETURN ZERO;
                                 when ONE|HIGH    =>  NULL;
                                 when others =>  RETURN UNKNOWN;
                               END CASE;
               when others =>  RETURN UNKNOWN;
            END CASE;
        END LOOP;
        RETURN ONE;
    else
        RETURN not Store;
    END IF;
END xnor_bw;
--
------------------------------------------------------------------------
--  Comparison Operators
------------------------------------------------------------------------
--
FUNCTION "=" (i1, i2: logic_mv) RETURN logic_mv is
     constant table: logic_mv_table :=
      ((UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN),
       (UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN),
       (UNKNOWN, UNKNOWN, ONE,     ZERO,    UNKNOWN, ONE,     ZERO),
       (UNKNOWN, UNKNOWN, ZERO,    ONE,     UNKNOWN, ZERO,    ONE),
       (UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN),
       (UNKNOWN, UNKNOWN, ONE,     ZERO,    UNKNOWN, ONE,     ZERO),
       (UNKNOWN, UNKNOWN, ZERO,    ONE,     UNKNOWN, ZERO,    ONE));
BEGIN
   RETURN table (i1,i2);
END "=";
------------------------------------------------------------------------

FUNCTION "/=" (i1, i2: logic_mv) RETURN logic_mv is
     constant table: logic_mv_table :=
      ((UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN),
       (UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN),
       (UNKNOWN, UNKNOWN, ZERO,    ONE,     UNKNOWN, ZERO,    ONE),
       (UNKNOWN, UNKNOWN, ONE,     ZERO,    UNKNOWN, ONE,     ZERO),
       (UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN),
       (UNKNOWN, UNKNOWN, ZERO,    ONE,     UNKNOWN, ZERO,    ONE),
       (UNKNOWN, UNKNOWN, ONE,     ZERO,    UNKNOWN, ONE,     ZERO));
BEGIN
   RETURN table (i1,i2);
END "/=";
------------------------------------------------------------------------

FUNCTION "=" ( i1,i2 :  logic_vector_mv )	RETURN logic_mv is
    alias Arg1 : logic_vector_mv (1 to i1'length) is i1;
    alias Arg2 : logic_vector_mv (1 to i2'length) is i2;
    variable Store : logic_mv;

BEGIN
    assert i1'length = i2'length report "Bus width mismatch" severity warning;
    FOR i in i1'range LOOP
        Store := Arg1(i) = Arg2(i);
        IF Store /= ONE then 
            RETURN Store;
        END IF;
    END LOOP;
RETURN ONE;
END "=";
------------------------------------------------------------------------

FUNCTION "/=" ( i1,i2 :  logic_vector_mv )	RETURN logic_mv is
    alias Arg1 : logic_vector_mv (1 to i1'length) is i1;
    alias Arg2 : logic_vector_mv (1 to i2'length) is i2;
    variable Store : logic_mv;

BEGIN
    assert i1'Length = i2'length report "Bus width mismatch" severity warning;
    FOR i in i1'range LOOP
        Store := Arg1(i) /= Arg2(i);
        IF Store /= ONE then 
            RETURN Store;
        END IF;
    END LOOP;
RETURN ONE;
END "/=";
--
-------------------------------------------------------------------------
--   Bus Resolution Functions
-------------------------------------------------------------------------
--
FUNCTION Wired_Outputs (signals : logic_vector_mv) RETURN logic_mv is
   VARIABLE  result : logic_mv := HIGHZ; -- return 'Z' when no active driver
   constant Table  : logic_mv_table :=
     ((UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN),
      (UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN),
      (UNKNOWN, UNKNOWN, ZERO,    UNKNOWN, ZERO,    ZERO,    ZERO),
      (UNKNOWN, UNKNOWN, UNKNOWN, ONE,     ONE,     ONE,     ONE),
      (UNKNOWN, UNKNOWN, ZERO,    ONE,     HIGHZ,   LOW,     HIGH),
      (UNKNOWN, UNKNOWN, ZERO,    ONE,     LOW,     LOW,     HIGHZ),
      (UNKNOWN, UNKNOWN, ZERO,    ONE,     HIGH,    HIGHZ,   HIGH));
BEGIN
    FOR i in signals'range LOOP
        result := table (result, signals(i));
        exit when result = UNKNOWN;
    end loop;
    RETURN result;
end Wired_Outputs;
--
--
FUNCTION Wired_Or (signals : logic_vector_mv) RETURN logic_mv is
   VARIABLE  result : logic_mv := HIGHZ; -- return 'Z' when no active driver
   constant Table  : logic_mv_table :=
     ((UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN),
      (UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN),
      (UNKNOWN, UNKNOWN, ZERO,    ONE,     ZERO,    ZERO,    ZERO),
      (UNKNOWN, UNKNOWN, ONE,     ONE,     ONE,     ONE,     ONE),
      (UNKNOWN, UNKNOWN, ZERO,    ONE,     HIGHZ,   LOW,     HIGH),
      (UNKNOWN, UNKNOWN, ZERO,    ONE,     LOW,     LOW,     HIGHZ),
      (UNKNOWN, UNKNOWN, ZERO,    ONE,     HIGH,    HIGHZ,   HIGH));
BEGIN
    FOR i in signals'range LOOP
        result := table (result, signals(i));
        exit when result = UNKNOWN;
    end loop;
    RETURN result;
end Wired_Or;
--
--
FUNCTION Wired_And (signals : logic_vector_mv) RETURN logic_mv is
   VARIABLE  result : logic_mv := HIGHZ; -- return 'Z' when no active driver
   constant Table  : logic_mv_table :=
     ((UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN),
      (UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN),
      (UNKNOWN, UNKNOWN, ZERO,    ZERO,    ZERO,    ZERO,    ZERO),
      (UNKNOWN, UNKNOWN, ZERO,    ONE,     ONE,     ONE,     ONE),
      (UNKNOWN, UNKNOWN, ZERO,    ONE,     HIGHZ,   LOW,     HIGH),
      (UNKNOWN, UNKNOWN, ZERO,    ONE,     LOW,     LOW,     HIGHZ),
      (UNKNOWN, UNKNOWN, ZERO,    ONE,     HIGH,    HIGHZ,   HIGH));
BEGIN
    FOR i in signals'range LOOP
        result := table (result, signals(i));
        exit when result = UNKNOWN;
    end loop;
    RETURN result;
end Wired_And;
------------------------------------------------------------------------
--
-------------------------------------------------------------------------
--   Miscellaneous Functions
-------------------------------------------------------------------------
--
--   FUNCTION name: Filter
--   parameters:
--       in   input    --  logic_mv -- data input present value
--   RETURNs:    - translated logic_mv state :
--                 ( HIGH -> ONE;
--                   LOW  -> ZERO;
--                   HIGHZ -> UNKNOWN )
--
--   purpose: Used to prevent HIGH, LOW and HIGHZ states on an input
--            from being stored and subsequently output from the model.
--
------------------------------------------------------------------------------
FUNCTION Filter (input : logic_mv) RETURN logic_mv is
   constant filter_table  : logic_mv_array :=
      (UNKNOWN, UNKNOWN, ZERO, ONE, UNKNOWN, ZERO, ONE);
BEGIN
   
RETURN filter_table(input);
END Filter;
--     
-----------------------------------------------------------------------
--  Signal transitions and relationships
-----------------------------------------------------------------------
--
------------------------------------------------------------------------------
FUNCTION Posedge( signal s1 : logic_mv ) RETURN boolean   is
begin

    RETURN s1 = ONE and s1'last_value = ZERO and s1'event;

end Posedge;
------------------------------------------------------------------------

FUNCTION Negedge( signal s1 : logic_mv ) RETURN boolean   is
begin
  
  RETURN s1 = ZERO and s1'last_value = ONE and s1'event; 

end Negedge;
------------------------------------------------------------------------

PROCEDURE Setup_check (constant input_le : time; constant time_spec : time; 
                constant message : string; constant err_level : severity_level)
  is

begin

  assert input_le >= time_spec
         report message & " setup violation" severity err_level;

end Setup_check;
------------------------------------------------------------------------

PROCEDURE Hold_check (constant input_le : time; constant time_spec : time; 
                constant message : string; constant err_level : severity_level)
  is

begin

 
    assert input_le > time_spec 
           report message & " hold violation" severity err_level;

end Hold_check;
------------------------------------------------------------------------

FUNCTION F_delay( newlv : in logic_mv; delay01 : in time; delay10 : in time) 
         RETURN time is
BEGIN 
    CASE newlv is
      when ZERO       => RETURN delay10;
      when ONE       => RETURN delay01;
      when others    => IF (delay01 > delay10)  then
                          RETURN delay01;
                        else
                          RETURN delay10;
                        END IF;
    END CASE;
  END F_delay;
--
--
END BASICDEFS;