Reserved Word and Predefined Attribute Listings

                                   excerpted from
                                 IEEE Standard VHDL
                              Language Reference Manual
                                 IEEE Std 1076-1987

                                 Copyright (c) 1988.
             The Institute of Electrical and Electronics Engineers, Inc.
             (Permission to reprint granted if above header is retained)


Reserved Words

abs	else	nand	select	
access	elsif	new	severity	
after	end	next	signal	
alias	entity	nor	subtype	
all	exit	not	 	
and	 	null	then	
architecture	file	 	to	
array	for	of	transport	
assert	function	on	type	
attribute	 	open	 	
 	generate	or	units	
begin	generic	others	until	
block	guarded	out	use	
body	 	 	 	
buffer	if	package	variable	
bus	in	port	 	
 	inout	procedure	wait	
case	is	process	when	
component	 	 	while	
configuration	label	range	with	
constant	library	record	 	
 	linkage	register	xor	       
disconnect	loop	rem	
downto	 	report	
 	map	return	        
 	mod


Predefined Attributes

'pos(x)	'val(x)	'base
'succ(x)	'pred(x)	'leftof(x)	'rightof(x)
'left	'right	'high		'low
'left[(n)]	'right[(n)]	'high[(n)]	'low[(n)]
'range[(n)]	'reverse_range[(n)]	'length[(n)]
'event	'active	'last_event	'last_active
'last_value	'behavior	'structure

'delayed[(t)]	'stable[(t)]	'quiet[(t)]	'transaction[(n)]