The hardware part of the programme is carried out by three companies, Matra MHS, Matra MMS and Saab Ericsson Space. Matra MHS will manufacture and market all three devices, and is designing the 90C601E and 90C602E. The MEC is defined by Saab Ericsson Space and designed by Matra MMS. The software part is carried out by Logica, Alsys and Spacebel. See paragraph "Available Documentation" for how to obtain more information about the ERC32 components and software tools.
ERC32 Development Milestones
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Date Milestone description
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Jun 1995 Samples of ERC32 devices
Sep 1995 ERC32 ADA cross-compiler system
Dec 1995 Radiation and life tests of ERC32 devices completed
Jan 1996 Real-time software analysis tools
Mar 1996 AJPO validation of ERC32 ADA cross-compiler system
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The development program has up to now concentrated on defining, specifying and simulating the ERC32 devices and a complete ERC32-based computer. All three devices have been modelled in VHDL and extensively simulated to verify correct operation. Maximum effort is now being put on detailed design and layout. The logic design and floorplan for 90C601E and 90C602E is completed and the work on layout generation and verification has been started. The MEC is currently being synthesized from VHDL and will be implemented on a MC-RT gate array. The layout of all three devices is planned to be completed in January 1995, after which the first set of prototypes will be manufactured. The first samples are expected end Q2 1995.
In complement to the ERC32 ACS, the ERC32 target simulator is primarily intended to support module testing, but it may also perform the timing characterization of application components. Access and commanding to the target simulator are possible both via the ACS debugger and in stand-alone mode. The ERC32 target simulator, which builds on the well-known Sparcsim package, is developed by Spacebel (B). Its first release integrated with the ERC32 ACS debugger is foreseen by Q4 1995.
The primary goal of the ERC32 software tool-set is to provide advanced support for the development of hard real-time Ada applications. Such provision consists of a combination of run-time and off-line features, specifically aimed at the support of the deadline-monotonic scheduling scheme. The run-time features (which effectively bridge Ada83 to selected real-time features of Ada9X) are directly supported by the ERC32 ACS. The off-line support is provided by a pair of tools for the deadline-monotonic scheduling analysis of Ada applications. Such tools, when input a schematic description of the application (essentially its timing attributes and requirements), predict the response time of the individual threads of execution in relation to the relevant deadline, and enable the user to inspect the corresponding (simulated) sequence of scheduling events. Both scheduling prediction and simulation take full account of the actual overheads to be experienced when running ERC32 Ada applications on ERC32 hardware based platforms. These tools, often referred to as hard real-time tools, are implemented by Spacebel. Their first release is expected by Q4 1995.
To minimize the risk for SEU (Single-Event Upset) induced errors, a special register cell has been used for all registers on the devices. This cell is designed to have high SEU immunity, tests have shown an LET of more than 30 MeV. In addition to the SEU resistant cells, dedicated error-detection logic is used on all devices, capable of detecting more than 99% of all SEU errors. Due to the pipelined architecture of the IU, many errors may be removed transparently through a instruction restart procedure. For more details on the error-detection mechanisms implemented in ERC32, please refer to "Available Documentation and Reports" on page 6.
In addition to the listed kernels, there is also Myth-Os from Florida State University. Myth-Os is a free, stand-alone kernel for SparcEngine 1E. It is based on Pthreads, also from FSU, which is a package implementing the POSIX thread extension (1003.1b). Check the WWW page of Frank Mueller for more information on Pthreads and Myth-Os. Plans are made to port Myth-Os to ERC32, and provide it free of charge for prototyping and tests.
Real-time kernels for SPARC
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Kernel name Features Supplier
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RTUX-EX Emerge Systems
C-Executive Partial POSIX JMI Software Systems
LynxOs POSIX 1003.1b Lynx Real Time Systems
VRTX/OS 3.0 Microtec Research SA
RTMX Full POSIX RTMX
SuperTask US Software,
VxWorks Partial POSIX Wind River Systems
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Compilers for SPARC
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Language Features Supplier
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C, C++, Fortran, Debugger Oasys
Pascal, ADA
C, C++ Debugger, Monitor Microtec Research SA
ADA Debugger Alsys France
Run-time kernel
ADA Debugger, runs on Rational/Verdix
top of VxWorks
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Get hold of a Sparcstation 1 or similar (FORCE, Themis etc.). Compile your application with the compiler of your choice and run it in native mode on the Sparcstation. Multiply the execution time with 1.1 and you will be within 10% of the ERC32 performance. If you use a Sparcstation 2, multiply with 2.3.
Get hold of GCC-2.6.0 and GNAT-1.8.3 (or higher). Install on your Sparcstation and - voilá - you have one of the best C compilers available together with a fairly complete ADA9X compiler (native). Alternatively, there are commercial host/host ADA compilers available from Alsys, Telesoft and Verdix just to mention a few.
To get your real-time application running in an UNIX environment, install VxWorks, LynxOs, RTX32 or even Solaris 2.3 on your Sparcstation or SPARC VME-board. If your application is written in ADA, use Verdix ADA which runs on top of VxWorks. For C applications, you can use almost any C-compiler and link with the run-time libraries provided by the OS. It can be useful to know, that if your application is using 1553-buses, there is a commercial SBus-board available with dual 1553-interfaces which plugs straight in into most Sparcstations. If you are using a VME-based SPARC-board, there are of course several types of interface boards available.
Get in contact with J.Gaisler at ESTEC/WDI. If your application is reasonably structured and documented, he could be persuaded to compile it and run it on a Sparcstation or ERC32 simulator.
This is a tricky one. Since the components are not yet available, you can start by obtaining the VHDL models from Matra MHS and then design and simulate your board in VHDL. The pin-out of the devices will be available in January 1995, after which you can make the final layout of your board. Port your monitor and other software using the VHDL model of your board and wait for the ERC32 prototypes (end Q2 1995). Alternatively, you can use the commercial 90C601/90C602 from MHS and design a limited MEC in a FPGA. In the later case however, my feeling is that by the time you have all things up and running, the ERC32 components will be available anyway.
Available documentation(a)
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Source Document
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MHS 90C601E - IU Device Specification
MHS 90C602E - FPU Device Specification
MHS MEC DeviceSpecification
MHS/ESTEC ERC32 Functional Specification
MHS/ESTEC ERC32 System Design Document
ESTEC ERC32 Error-detection and fault-tolerance (FTCS-24 conference paper)
ESTEC ERC32 Benchmark report
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SPARC product vendors ------------------------------------------------------------------------------------------------- Company Contact person Products/Functions ------------------------------------------------------------------------------------------------- Alsys SA, 29 Avenue Lucien René Duchesne, J-L Goutagny ADA compilation 78170 La Celle Saint-Cloud, France goutagny@alsys.fr system +31-1-30781730, FAX: +31-1-39182680Emerge Systems, 3950 Dow Rd. Unit D Melbourne RTUX-EX kernel FL 32934, USA, (407)259-1165
ESA/ESTEC, Postbus 299, 2200 AG Noordwijk, Jiri Gaisler ERC32 technical The Netherlands, +31-1719-84880, jgais@wd.estec.esa.nl officer email: jgais@wd.estec.esa.nl
JMI Software Systems, 904 Sheble Lane, Spring C-Executive House, PA 19477, USA, (215)621-0840
Lynx Real Time Systems, 16780 Lark Avenue, Los sales@lynx.com LynxOs Gatos, CA 95030, USA, (800)327-5969
Matra MHS SA, 3 Avenue du Centre, BP 309, Amar Guennon ERC32 components 78054 St-Quentin-en-Yvelines, Cedex, France amar.guennon@matramhs.fr and VHDL models +31-1-30607087 FAX: +31-1-30640693
Microtec Research SA, Immeuble le Sésame, 8 rue Michel Limonet C/C++ Compiler Germain Soufflot, 78184 Saint-Quentin en Yve VRTX kernel lines CEDEX, France, +33-1-30120210, FAX: +33-1-30120220
Oasys, One Cranberry Hill, Lexington, Massachu David W. Chandler C, C++, Fortran, Pas setts 02173, USA, (617)862-2002, FAX: (617)863- cal and ADA compil 2633 ers
Rational Software Corporation, 2800 San Tomas Verdix ADA com Expressway, Santa Clara, CA 95051-0951, USA piler email: product_info@rational.com
RTMX, 333 Chapel Hill Blvd., Suite D200 RTMX kernel Durham, MC 27707, USA, (919)493-1452
US Software, 14215 NE Science Park Dr., Portland SuperTask OR 97229, USA, (503)641-8446
Wind River Systems, 27 Avenue de la Baltique, VxWorks Bâtiment B4, LP739 Z.A. de Courtaboeuf, 91962 Les Ulis, Cedex, France. +31-1-69077878 FAX: +31-1-69070826 -------------------------------------------------------------------------------------------------