Evaluation within the 32-bit microprocessor project

Hardware evaluation ERC32 chipset : IU, FPU and MEC

Software development Alsys ERC32 Ada compiler and debugger

Hardware evaluation ERC32 computer core running since Oct-95

VHDL system level simulations since Sept-95

Software development Ada compiler and debugger development on

DEM32 since Nov-95

* RISC architecture based on the ERC32 processor core: IU, FPU and MEC

* Ada TAsking Coprocessor (ATAC)

* Fault tolerance support by concurrent error detection with high coverage, including error detection and correction (EDAC) of memory transfers

* Two RS232C standard serial ports for program download and debug.

* 2 Mbyte RAM expandable to 4 Mbyte RAM, and 2 MByte redundant RAM

* 128 kbyte start-up EEPROM

* Monitor for program download and debug

* System clock frequency 10 MHz, 0 Waitstate => ~ 7 Mips

Software development Alsys ERC32 Ada compiler or GNU C/C++ compiler

Software debug Alsys ERC32 Ada debugger on target or
GNU C/C++ debugger on ERC32 simulator

HW debug Test connector on internal buses

Target download Monitor / UART RS232

Hardware requirement RS232 and Power from VME crate

Hardware evaluation DEM32 V.1 SES Oktober 1995
DEM32 V.2 SES June 1996

Software development DEM32 V.1 Alsys Oktober 1995
DEM32 V.2 Alsys June 1996

Software evaluation DEM32 V.3 ESTEC December 1996
DEM32 V.3 ESTEC December 1996
DEM32 V.3 ESTEC December 1996

Hardware design Straight on interface between circuits

Wide variety of RAM organisations

Minimal Boot-strap requirement

Minimal support logic requirement

Hardware test/debug System error handler

Fault and error status registers

Error injection

On-line documentation http://www.estec.esa.nl/wsmwww/erc32/docs.html

Other documentation DEM32 V.2 USER´S MANUAL