FAQ comp.lang.vhdl part 1

comp.lang.vhdl
Frequently Asked Questions And Answers: Part 1

Preliminary Remarks

This is a monthly posting to comp.lang.vhdl containing general information. Please send additional information directly to the editor:

edwin@ds.e-technik.uni-dortmund.de (Edwin Naroska)

You can also use this form to drop me a short note if your client can handle FORMs.

Corrections and suggestions are appreciated. Thanks for all corrections.

There are three other regular postings: part 2 lists books on VHDL, part 3 lists products & services (PD+commercial), part 4 contains descriptions for a number of terms and phrases used to define VHDL.

0. General Information/Introduction
1. Abbreviations
2. Contacts and Archives
3. VHDL on the Web
4. Frequently Asked Questions

0. General Information/Introduction

0.1 The Group - Why and What

The newsgroup comp.lang.vhdl was created in January 1991. It's an international forum to discuss ALL topics related to the language VHDL which is currently defined by the IEEE Standard 1076/93. Included are language problems, tools that only support subsets etc. NOT other languages such as Verilog HDL. This is not strict - if there is the need to discuss information exchange from EDIF to VHDL for example, this is a topic of the group. The group is unmoderated. Please think carefully before posting - it costs a lot of money! (Take a look into your LRM for example - if you still cannot find the answer, post your question, but make sure, that other readers will get the point). A chapter for frequently asked questions about the language will later be added to this regularly posted information - as they appear on the net. If necessary for the amount of information, this posting will possibly be split into separate postings for each chapter.

0.2 What Is VHDL

VHDL-1076 (VHSIC (Very High Speed Integrated Circuits) Hardware Description Language) is an IEEE Standard since 1987. It is "a formal notation intended for use in all phases of the creation of electronic systems. ... it supports the development, verification, synthesis, and testing of hardware designs, the communication of hardware design data ..." [Preface to the IEEE Standard VHDL Language Reference Manual] and especially simulation of hardware descriptions. Additionally VHDL-models are a DoD requirement for vendors.

Today simulation systems and other tools (synthesis, verification and others) based on VHDL are available. The VHDL users community is growing fast. Several international conferences organized by the VHDL Users Groups(s) have been held with relevant interest. Other international conferences address the topic with growing interest as well (Conference on Hardware Description Languages -CHDL-, [European] Design Automation Conference -[Euro]DAC ...).

0.3 Before Posting

- read the 4 FAQ's - they possibly answer your questions
- question about the language: try to find out in your LRM

0.4 Major Contributors to this FAQ

The basic version of this FAQ was created by Tom Dettmer.
Thanks to Georg Staebner for his work on part 4.

1. Abbreviations

AHDL:: Analog Hardware Description Language
BBS:: Bulletin Board System
DoD:: USA Department of Defense
FAQ:: Frequently Asked Questions
IEEE:: The Institute of Electrical and Electronics Engineers. In case of VHDL, they defined the standard 1076
LRM:: Language Reference Manual
TISSS:: Tester Independent Support Software System
VASG:: VHDL Analysis and Standardization Group
VFE:: VHDL Forum Europe
VHDL:: VHSIC Hardware Description Language
VHSIC:: Very High Speed Integrated Circuits - A program of the DoD
VI:: VHDL International
VIUF:: VHDL International Users Forum
VUG:: VHDL Users Group, see below
WAVES:: Waveform Vector and Exchange Specification, proposed IEEE Standard

2. Contacts and Archives

2.1 Official Contacts

VHDL International

The web site of VHDL International (VI) is at http://www.vhdl.org/vhdl_intl/. The contact address is

VI Membership & Administration, Tel: (408) 492-9806, viadmin@vhdl.org

Current Groups on the VHDL International Users Forum System (4 Feb 1997, ver 2.2) - an actual version of this list can be found at http://www.eda.org/ or ftp://vhdl.org/pub/docs/groups.txt


Name                                                     code-name
-------------------------------------------------        ------------
3D TCAD Modeling Interoperability                        tcad3d
Bay Area MEMS Journal Club                               bamjc
EIA DAD Advanced Intermediate Rep. with Extensibility    aire
EIA DAD DIE ((bare) Die Info Exchange) Format            die
EIA DAD IBIS Open Forum (I/O Buffer Info Spec)           ibis
EIA DAD Microwave Design Automation Standards            microwave
EIA DAD Rule Augmented Interconnect Layout Specification rail
EIA DAD VHDL Commercial Component Model Spec             eia567
Free Model Foundation                                    fmf
Free VHDL Products from MTL Systems for Non-commer use   mtl
HDL Conference (old IVC and Spring VIUF)                 hdlcon
IEEE Design Automation Standards Committee               dasc
IEEE DASC Chip Hierarchical Design System tech. data WG  chdstd
IEEE DASC Circuit Delay and Power Calculation System     dpc
IEEE DASC High Performance HDL Simulation WG             hpm-sim
IEEE DASC HW/SW Codesign SG                              codesign
IEEE DASC Open Modeling Forum WG                         omf
IEEE DASC Standard Delay Format SG                       sdf
IEEE DASC System Design & Description Language SG        sddl
IEEE DASC Timing (VHDL Intiative Towards ASIC Libraries) vital
IEEE DASC VASG ISAC (VHDL)                              *isac
IEEE DASC Verilog WG                                     1364
IEEE DASC VHDL Analog Extensions WG                      analog
IEEE DASC VHDL Library "library ieee;" WG                libieee
IEEE DASC VHDL Library - Utility WG                      libutil
IEEE DASC VHDL Math Package WG                           math
IEEE DASC VHDL Microwave SG                              vhdl-mw
IEEE DASC VHDL Object Oriented SG                        oovhdl
IEEE DASC VHDL Parallel Simulation WG                    parallel
IEEE DASC VHDL Shared Variable WG                        svwg
IEEE DASC VHDL Synthesis WG                              vhdlsynth
IEEE DASC VHDL Test WG                                   vhdl_test
IEEE DASC / SCC20 Waveform and Vector Exchange Std       waves
OVI/VI Synthesis Constraints WG                          scwg
VHDL International (VI)                                 *vi
VHDL International Users' Forum (old VHDL Users' Group) *viuf
VHDL Validation Suite Effort                             validation
VI Marketing Advisory Committee                          mac
VI Technical Advisory Committee                          tac
VIUF Local Chapter - Boston, MA                          boston_lc
VIUF Local Chapter - Mid-West                            midwest_lc
VIUF Local Chapter - Phoenix, AZ                         phoenix_lc
VIUF Local Chapter - Denver, CO                          rockymnt_lc
VIUF Local Chapter - Sacramento, CA                      sac_lc
VIUF Local Chapter - San Diego, CA                       sandiego_lc
VIUF Local Chapter - Silicon Valley (Local Users Group)  svlug
VIUF Local Chapter - Southern California                 socal_lc

* General email exploder / discussion group not available

(note: You can substitute verilog.org, hdlcon.org or eda.org for vhdl.org)

To find out more info about a group, send an email request to:

        -info@vhdl.org

To get added to an email exploder and be made aware of the groups
activities, send your email address to:

        -request@vhdl.org

To submit a message to an email exploder, email the message to:

        @vhdl.org

Most of these groups have active file repositories also (including an
archive of all email discussion traffic).  Check either the "pub"
directory for the group of interest.

Teaser packets of information (just to get your feet wet) exist on this
repository for the following groups.  (You need to check the home
Internet FTP servers or use Gopher to get the up-to-date and complete files.)

EDIF Technical Center, University of Manchester         pub/edif-tc
ISO TC184/SC4/WG4, etc. (STEP Standard)                 pub/iso10303
ISO TC184/SC4/WG2 - Part Libraries STEP Application     pub/iso13584

In addition, there are repositories for the following topics / ad-hoc groups:

Misc. submissions (from VUG/VIUF meetings, etc.)        vi/misc
VHDL Users' Group RBBS PC Machine (1988-1991)           vi/vug_bbs
Useful public domain tools for UNIX, Macintosh, and     pub/tools
  PC (DOS and Windows)

You may also join an on-line discussion group via http://www.vhdl.org/vhdl_intl/viis-info.html

VHDL-Forum for CAD in Europe (VFE)

The VHDL-Forum for CAD in Europe is the European users group active in VHDL related topics & standardization efforts. VFE is open to all interested participants. Contact:

Andreas Hohl (Chair) SIEMENS, Dept. ZFE IS EA Ref Otto-Hahn-Ring 6 81739 Munich Germany Phone: +49-89-636-41895 Fax: +49-89-636-44950 Email: ah@ztivax.siemens.com

VHDL Newsletter

Editor of the US Newsletter: contact
Allen M. Dewey adewey@vnet.IBM.COM
Europe Editor of the European Newsletter: contact
J. Mermet, J. Rouillard, Phone: 3+91 05 44 44, FAX 33+91 05 43 43, Institut Mediterraneen de Technologie Technopole de Chateau-Gombert, 13415 Marseille cedex -FRANCE-

Mail items of interest to info-vhdl@thor.ece.uc.edu (129.137.8.118)
Mail a request to be added to the group of registered news subscribers to
info-vhdl-request@thor.ece.uc.edu

AHDL, 1076.1 Working Group

The purpose of 1076.1 Working Group (WG) is to develop analog extensions to VHDL, i.e. to enhance VHDL such that it can support the description and simulation of circuits that exhibit continuous behavior over time and over amplitude. As of summer 1993 the IEEE Computer Society, through its Standards Activity Board (SAB), has approved the 1076.1 WG under PAR1076.1.

     1076.1 Executive Committee
        Working Group Chair & Secretary: 
                Alain Vachoux
                Swiss Federal Institute of Technology
                Integrated Systems Center
                CH-1015 Lausanne, Switzerland
                Phone: +41 21 693 6984
                Fax: +41 21 693 4663
                Email: alain.vachoux@epfl.ch 
        Working Group Vice-Chair: 
                Ernst Christen
                Analogy Inc.
                P.O. Box 1669
                9205 SW Gemini Drive
                Beaverton, OR 97075-1669, USA
                Phone: (503) 520-2720
                Fax: (503) 643-3361
                Email: christen@analogy.com 
     1076.1 Mailing List
        Reflectors (information to all members of the mailing list):
                1076-1@epfl.ch                  European address
                ahdl1076@cadence.com            US address
        Submit new names to be put on the mailing list to
                1076-1-request@epfl.ch
        Submit to 1076.1 Executive Committee only:
                1076-1-exec@epfl.ch
     1076.1 Repositories:
        ftp://vhdl.org/pub/analog/ftp_files/

See Section 4.5 and http://www.vhdl.org/analog/ for further information.

WAVES/TISSS

Standard for VHDL Waveform and Vector Exchange (WAVES). See http://www.vhdl.org/waves/ for further information.

2.2 VHDL User Groups

VHDL International Users Forum

The first (VUG) was transformed into the second (VIUF) in 1991. VIUF is Chaired by Praveen Chawla and is a chapter and thus sponsored by VHDL International (VI). They organize conferences and have some other activities.

WWW: http://server.vhdl.org/viuf/
Email: viuf-info@vhdl.org

French (speaking) VHDL User's Group

The french (speaking) VHDL Users' Group is actually a 'French-Speaking' due to the presence of Swiss people. (Belgium, Luxemburg and Val d'Aoste people are welcome). Organization is taken in charge by

Roland Airiau - airiau@cns.cnet.fr

Jean-Michel Berge - berge@cns.cnet.fr

Serge Maginot - serge.maginot@vhdl.org

Alain Vachoux - alain.vachoux@leg.de.epfl.ch

The first meeting was in Grenoble, November 30th, 1993. There were around 45 people. The meeting was quite good.

German speaking VHDL User's Group

Sabine.Maerz@zfe.siemens.de

maintains the mailing list and manages the group.

Russian VHDL Interest Group

Prof. Tartanikov Information Systems Research Institute 129090 Moscow Shchepkina 22, RUSSIA email: yat@hq.isrir.msk.su, FAX: +7-095-288-18-61

VHDL User's Group of Belarus

Dr. Anatoly Prihozhy Institute of Engineering Cybernetics Academy of Sciences of Belarus 6 Surganov Str. 220012 Minsk, Republic of Belarus FAX ++7(0172)318403, email: mahaniok@adonis.iasnet.com

UK VHDL User's Group

Lucas Advanced Engineering Centre - Dog Kennel Lane Shirley - Solihull, W. Midlands B90 4JJ - England phone: +44-21-627-4141, FAX: +44-21-627-3584 email (newsletter): kgh@lishirl1.li.co.uk

VHDL Users Group of Spain

President: Serafin Olcoz, email: Serafin.Olcoz@sp1.y-net.es Secretary: Eugenio Villar, email: villar@melst1.unican.es

2.3 Archives

Archives:

The FAQ is also available by ftp on vhdl.org /pub/comp.lang.vhdl/FAQ* see VHDL International for details on accessing the server. They also plan an archive of the groups articles.
You can find this FAQ at (USA) http://vhdl.org/comp.lang.vhdl/
The ACM SIGDA (Special Interest Group Design Automation) offers through a gopher server a large amount of info, besides other stuff, the FAQ of this group and an archive dating back to 1992. These services, and many others, are available via the ACM SIGDA Internet Server Project - http://kona.ee.pitt.edu/
archives for this newsgroup: http://kona.ee.pitt.edu/NewsGroupArchives/comp.lang.vhdl/index.html
Updated versions of the various DA-related FAQ's: http://kona.ee.pitt.edu/NewsGroupArchives/NewsGroupArchives.html
There are collections of interesting tidbits from all of the DA Newsgroups at URL: http://kona.ee.pitt.edu/CollectedInformation/NewsgroupHighlights/NewsgroupHighlights.html

3. VHDL on the Web

Here are some useful links on the web related to VHDL. If you discover an interesting server not mentioned in this list or a link is broken please send a note to the editor.

3.1 Tutorials

Accolade Design Automation, by David Pellerin: http://www.acc-eda.com/h_intro.htm
The tutorial gives an overview of the language and its uses for synthesis and simulation.
Green Mountain Computing Systems: http://homepages.together.net/~thibault/tutorial.htm
VHDL Synthesis Tutorial by Bob Reese, Electrical Engineering Department Mississippi State University: http://www.erc.msstate.edu/~reese/vhdl_synthesis/
A VHDL Synthesis Tutorial, by Michael Gschwind and Valentina Salapura: http://www.vlsivie.tuwien.ac.at/mike/vhdl4fpga/default.htm
Logic Synthesis Using VHDL by Dimitris Phoukas: http://silicon.vlsi.uwindsor.ca/tutorials/VHDLsynthTutorial/index.html
Introduction to VHDL, US. Army: http://fcim.csdc.com/fcimis/vhdltutr/vhdlintro.html
Introduction to VITAL '95 by Steve Schulz: http://vhdl.org/vi/vital/wwwpages/steves/
VHDL-Modelling And Synthesis Of The DLXS RISC Processor by Martin Gumm, University of Stuttgart: ftp://ftp.informatik.uni-stuttgart.de/pub/vhdl/vlsi_course/
Doulos High Level Design Web site; A Hardware Engineers Guide to VHDL: http://www.doulos.co.uk/hegv/index.htm
Synthesis tutorial from Park Chang Wook (not very much text but several small examples): http://eecad.sogang.ac.kr/~chang/vhdl
Synthesis Tips for Xilinx Users: http://www.acc-eda.com/xplus.htm
VHDL Synthesis Tutorial from APS: http://www.associatedpro.com/aps/x84lab/
Interactive VHDL Tutorial from Aldec, Inc.: http://www.aldec.com/pages/free.htm
FPGA Synthesis by Scott E. Harrington: http://www.ee.duke.edu/Research/VHDL_tutorial/
Waveform and Vector exchange Specification (WAVES) Tutorial: http://www.mtl.com/projects/waves/glup.html
VHDL Tutorial by Ulrich Heinkel and Martin Padeffke (in English and German): http://www.vhdl-online.de/~vhdl/TUTORIAL/

3.2 VHDL Models

The following links point to some servers containing "non commercial" VHDL models. Note, there may be some limitations and restrictions concerning the use of this software.

Microsystems Prototyping Laboratory: http://www.erc.msstate.edu/mpl/vhdl/html/models/
Microsystems Prototyping Laboratory Static RAM Generation Tool: http://WWW.ERC.MsState.Edu/mpl/vhdl/html/tools/sramgen/index.html
Free Modeling Foundation (FMF): http://vhdl.org/fmf/
The Hamburg VHDL archive: http://tech-www.informatik.uni-hamburg.de/vhdl/vhdl.html
RASSP www site: http://rassp.scra.org/vhdl/models.html
University of Strasbourg: http://erm1.u-strasbg.fr/db/ or ftp://erm1.u-strasbg.fr/pub/vhdl/
Doulos High Level Design Web site; Monthly-updated Original Models (developed by Doulos): http://www.doulos.co.uk/models/index.htm
Another pipelined version of the DLX may be found at: http://www.informatik.uni-stuttgart.de/ipvr/ise/projekte/dlx/
EDIF LPM - Library of Parameterized Modules: http://www.edif.org/edif/lpmweb/
A model for the ERC32 processor (a radiation-tolerant SPARC V7 version) from the ESA (European Space Agency): http://www.estec.esa.nl/wsmwww/erc32/
Public Ada Library: http://wuarchive.wustl.edu/languages/ada/pal.html
Micron Technology, Inc. (memorys): http://www.micron.com/mti/
U.C.I. HLSynth92: http://www.ics.uci.edu/pub/HLSynth92/
U.C.I. HLSynth95: http://www.ics.uci.edu/pub/HLSynth95/
Iopsys: http://www.iopsys.ru
IFIP WG10.5 Benchmark Circuits: http://goethe.ira.uka.de/hvg/benchmarks.html
A model of the DLX processor from P. Ashenden and an appropriate assembler: http://www.cs.adelaide.edu.au/users/petera/designers-guide/DG.html
A VHDL synthesizable model for the MICROCHIP PIC 16C5X microcontroller by Tom Coonan: http://www.mindspring.com/~tcoonan/
VHDL Model of the 8051 Microcontroller by Michael Mayer and Dr. Hardy J. Pottinger: http://www.ee.umr.edu/~mrmayer/8051/

Here are some links to commercial model sites:

4i2i Communications Ltd: http://www.4i2i.com/cores.htm
CAST, Inc.: http://www.cast-inc.com/
Comit Systems, Inc.: http://www.comit.com/
Denali Software, Inc.: http://www.denalisoft.com/
INICORE AG: http://www.inicore.ch/inicore/
Iopsys: http://www.iopsys.ru
Logic Innovations : http://www.logici.com/
Oxford Semiconductor Ltd: http://www2.oxsemi.com/
PALMCHIP: http://www.palmchip.com/
Richard Watts Associates Ltd : http://www.evolution-uk.com/rwa.html
Sand Microelectronics, Inc.: http://www.sandmicro.com/
Synopsys, Inc.: http://www.synopsys.com/
Technical Data Freeway, Inc.: http://www.tdf.com/
VAutomation, Inc.: http://www.vautomation.com/
Viewlogic's on-line CAE/CAD model library information center: http://www.viewlogic.com/ModelSite/
Virtual Chips, Inc.: http://www.vchips.com/
Papillon Research Corp.: http://www1.shore.net/~papillon/
Sapien Design, Inc.: http://www.sapiendesign.com/
A list of Software-Based Megacells and Cores (various vendors): http://www.isdmag.com/EEdesign/SoftCoretables.html
Sierra Circuit Design, Inc.: http://www.teleport.com/~scd

For other commercial model vendors see FAQ part 3 products & services.

3.3 Magazines

EE-Times: http://techweb.cmp.com/eet/823/
VHDL Times On-Line: http://vhdl.vhdl.org/vhdl_intl/vltimes/
CADENCE plugged-in: http://www.cadence.com/
The APS EDA Newsletter: http://www.associatedpro.com/aps/
Programmable Logic News & Views: http://www.plnv.com/

3.4 VHDL Sites

VHDL International Users' Forum (VIUF) Internet Services machine: http://vhdl.org/
The Hamburg VHDL archive: http://tech-www.informatik.uni-hamburg.de/vhdl/vhdl.html
Doulos High Level Design Web site: http://www.doulos.co.uk/
RASSP WWW site: http://rassp.scra.org/
VHDL UK: http://www.vhdluk.org/
University of Strasbourg: http://erm1.u-strasbg.fr/db/ or ftp://erm1.u-strasbg.fr/
VHDL International: http://www.vhdl.org/vhdl_intl/
VHDL Technology Group: http://www.vhdl.com/
ESA (European Space Agency): http://www.estec.esa.nl/wsmwww/vhdl/vhdlpage.html
University of Cincinnati: ftp://ftp.ececs.uc.edu/pub/vhdl
Programmable Logic Jump Station: http://www.optimagic.com

See also FAQ part 3 products & services for other VHDL vendor sites.

4. Frequently Asked Questions

There's not much until today - but I included those questions I've often heard from beginners. If someone feels, that a point should be included, please let me know.

4.1 About Changes to the VHDL Standard

According to IEEE rules every five years a standard has to be reproposed and accepted. This can include changes. Because VHDL is relatively young, the restandardization in 1992 included changes, and it will in 1997.

Changes in VHDL93 include: groups, shared variables, inclusion of foreign models in a VHDL description, operators, support of pulse rejection by a modified delay model, signatures, report statement, basic and extended itentifiers, more syntactic consistency.

4.2 Language Related Questions

This chapter tries to answer some questions about language details which appear more or less regular on the net.

4.2.1 USE of Library Llements?

Often users believe, they can use names of libraries /= work by simply inserting a use clause in the source. The analyzer responds with error messages. Insert a library clause before the use clause and all should work fine (See your LRM or FAQ Part 4 - B.74 for details).

4.2.2 GENERATE Usage and Configuration

The generate statement (FAQ Part 4 - B.105) is a concurrent statement (FAQ Part 4 - B.44) that contains other concurrent statements. Two forms exist: for and if generate. Example which uses both: First: if i=0 generate Q: adder port map (A(0), B(0), Cin, Sum(0), C(0)); end generate; G: for i in 1 to 10 generate Q: adder port map (A(i), B(i), C(i-1), Sum(i), C(i)); end generate; The components are addressed (e.g. for specification): First.Q, G(1).Q to G(10).Q Note: that form is used in an external configuration. If you need it inside you have to insert a block (FAQ Part 4 - B.136) in the generate statement and place your configuration specification within that block (see attribute application).

If you have a VHDL'93 compliant tool, things are easier.

4.2.3 Aggregates/Arrays Containing a Single Element

The question is often, whether SUBTYPE one_element IS bit_vector(1 TO 1); -- array containg only one element TYPE single IS RECORD a : INTEGER; END RECORD; SIGNAL o: one_element; SIGNAL s: single; ... s <= 1; -- first illegal try to assign a value to the record s <= (1); -- second try, also not legal in VHDL o <= '1'; -- first illegal try to assign a value to the array o <= ('1'); -- second try, also illegal is valid VHDL? It isn't. "Aggregates containing a single element association must always be specified using named association in order to distinguish them from parenthesized expressions." says the LRM. Therefore, "(1)" is simply a parenthesized expression (equal to "(((1)))"). s <= (a => 1); -- ok o <= (1 => '1'); -- ok; o <= (others => '1'); -- also ok, if the context makes it clear that -- there is only one element is valid. See FAQ Part 4 - B.7 for more information on aggregats.

4.2.4 How to Attach Attributes Inside of Generate

The '87 LRM is a bit confused as to whether the generate statement forms a declarative region, so it does not make provision for a declarative part in the syntax. However, it was decided that it indeed does form a declarative region (FAQ Part 4 - B.56), so in the '93 LRM we also included the syntax extension necessary for a declarative part. For '87, however, there is no such declarative part. The canonical method is to use an embedded block statement: G1:for i in DataIn'Low to DataIn'High generate b: block -- PJM addition attribute foo of RECV: label is 42; -- PJM addition begin -- PJM addition RECV:CHVQA; [simplified-PJM] end block b; -- PJM addition end generate ; cited from an article of Paul Mechini.

4.2.5 Notes on Range Directions

Let signal r3, r4: Bit_Vector(3 downto 0); ... r3(0 to 1) <= r4(0 to 1) ; Note the inverse direction of range (FAQ Part 4 - B.193) and aggregates (FAQ Part 4 - B.7). The 87 LRM does not clarify, if this is legal, but the official interpretation of the 87 language (VASG) says that the directions of slices must match the direction of the array being sliced. So it is not legal code. This decision is reflected in the VHDL'93 LRM.

Another, related problem is

signal r3, r4: Bit_Vector(3 downto 0); ... r3(0 downto 3) <= r4(0 downto 3) ; This code is legal. These slices are null slices (FAQ Part 4 - B.167). An array value of no elements (i.e., having a 'LENGTH of 0, FAQ Part 4 - B.165) can be assigned to an array having no elements, as long as their types are the same.

4.2.6 Integer - Time Conversion

The following example converts integer (FAQ Part 4 - B.134) to time (FAQ Part 4 - B.182) and time to integer. architecture convert of x is signal a,c : integer:=20; signal b : time; begin process begin wait for 1 fs; a <= a + 1; b <= a * 1 fs; wait for 1 fs; c <= b / 1 fs; end process; end;

4.2.7 "Don't Cares" in VHDL

The names given to the states (be it X, Z, don't care, even 0 and 1) of an enumeration type (FAQ Part 4 - B.85) have only the meaning brought by the subprograms of the package that defines the type. For example, 0 is 0 only because of the way "and", "or", etc, are written. Z is 'high impedance' and X is 'conflict' only because of the way the package, and particularly the resolution function is written. As for the "don't care", it has no particular meaning for simulation, and the STD_LOGIC package does not provide any semantics for it: it's a normal state.

For example in a case statement like

variable address : std_logic_vector(5 downto 0); ... case address is when "-11---" => ... when "-01---" => ... when others => ... end case; a 'address' value of "111000" or "101000" will match the 'others' clause! Here is a solution to this problem: if (address(4 downto 3)="11") then ... elsif (address(4 downto 3)="01") then ... else ... end if; Another solution is to use the "std_match" functions defined in the numeric_std package (see section 4.7): if (std_match(address, "-11---") then ... elsif (std_match(address, "-01---") then ... else ... end if; Partially extracted from an article of Jacques Rouillard.

4.2.8 How to Open and Close Files

The answer depends on which version of the language you're using. In VHDL'87, files cannot be opened and closed under model control. Instead the file object must be re-elaborated (see FAQ Part 4 - B.81). The following example shows how access a file via a procedure: -- VHDL'87 example! -- note the file is opend when get_file_data is called and closed -- when it returns! procedure get_file_data(file_name : in string) is type int_file_type is file of integer; -- see FAQ Part 4 - B.99 file file_identifier : int_file_type is in file_name; -- open file begin ... -- read in the file return; -- note, the file is closed now! end get_file; ... get_file_data("file1"); -- reads in the file named "file1" Additioanlly, in VHDL'93 it is possible to open and close files under model control via file_open(...) and file_close(...).

Note that the syntax rule for file declaration in VHDL'87 and VHDL'93 are different. Moreover, the VHDL'87 syntax rule is not a subset of the corresponding VHDL'93 syntax rule.

File declartion in VHDL'87:

type integer_file is file of integer; -- The following two declarations open a file for reading file file_ident1 : integer_file is "a_file_name1"; file file_ident2 : integer_file is in "a_file_name2"; -- The next declaration opens a file for writing file file_ident3 : integer_file is out "a_file_name3"; File declaration in VHDL'93: type integer_file is file of integer; -- The following two declarations open a file for reading file file_ident1 : integer_file is "a_file_name1"; file file_ident2 : integer_file open read_mode is "a_file_name2"; -- The next declaration opens a file for writing file file_ident3 : integer_file open write_mode is out "a_file_name3"; -- The next declaration opens a file for appending file file_ident4 : integer_file open append_mode is out "a_file_name4"; -- Finally, in VHDL'93 it is possible to declare a file identifier -- without associating it with a file name directly. Use -- file_open(...) and file_close(...) to open/close the file. file file_ident5 : integer_file;

4.2.9 How to Read/Write Binary Files

The file formats for binary files read or written by VHDL are not standardized. However, each simulator should be able to read its own generated binary files. This gives you two choices:

Write a pre/post-processor to convert binary files into text files and vice versa. Text files can be read/written by VHDL using the TEXTIO package.
Analyze the binary, which is generated by the simulator and then in turn generate binary according to that format. Usually, binary files written by VHDL start with a header followed by the actual data part. The header contains some release and/or type information. However, there is at least one simulator which doesn't create a header.

Partially extracted from an article posted by Wolfgang Ecker.

4.3 PUBLIC DOMAIN Tools?

Actually as far as I know, there is only few PD software on VHDL. If YOU know about something, please let us know. See products posting for more detailed information.

4.4 VHDL Validation Suite Available?

Yes. The latest version of the test validation suite is available via anonymous ftp://vhdl.org/pub/validation/vi_suite.tar.Z The current suite covers 36% of VHDL-1987. See http://www.vhdl.org/validation/ for further information.

4.5 Status of Analog VHDL (AHDL, 1076.1)

The draft 1076.1 Language Reference Manual has been successfully balloted during August-October 1997. The revised draft 1076.1 Language Reference Manual that incorporates the changes from the BRC (Ballot Resolution Committee) work is available for downloading at http://www.eda.org/analog/.

4.6 How Can People Get More Information about AHDL (1076.1)

The 1076.1 study group is maintaining an email bulletin board for distribution of announcements and as a forum for technical discussions. see above (official contacts).

4.7 Where Can I Find Standard Packages and More Info on Standards

Actually as far as I know no complete list with addresses of all documents exists. In general it's a good idea to look at the vhdl.org ftp server, fetch the most actual version of the groups list: /docs/groups.txt (see also Official Contacts ... above). The short names listed there are usually also used as directory names at vhdl.org - just look for /vi/ or /pub/. Somewhere below your chance to find the actual working documents is very good.

If someone has a partial or complete list, please send it to the author. I'll incorporate it here, if possible. Here is, what I have:

The IEEE 1164 std_logic package (std_logic_1164): http://vhdl.org/vi/libutil/utilities/gen_functions/IEEE1164
VHDL 1076.3 Bit Logic based synthesis package (numeric_bit): http://vhdl.org/vi/vhdlsynth/numeric_bit.vhd
VHDL 1076.3 Std_Logic_1164 based synthesis package (numeric_std): http://vhdl.org/vi/vhdlsynth/numeric_std.vhd
VITAL '95 Packages: http://vhdl.org/vi/vital/
WAVES 1997 Packages: http://vhdl.org/vi/waves/wwwpages/packages_1997.html
IEEE MATH_REAL Package (DRAFT!) containing log, sin,...: http://tech-www.informatik.uni-hamburg.de/vhdl/packages/mathpack/mathpack.vhd

4.8 Where to Obtain the comp.lang.vhdl FAQ

http://vhdl.org/comp.lang.vhdl/

(See also here)

4.9 Where Can I Find More Info

Of course, there are the other three parts of this FAQ.

Other good starting points are http://www.vhdl.org/docs/groups.txt or section 3. VHDL on the Web.

If other Resources should be listed here, please let me know.

Part 2: books on VHDL

Authors:

Tom Dettmer, Edwin Naroska

comp.lang.vhdlFrequently Asked Questions And Answers: Part 1

Table of Contents

VHDL International

comp.lang.vhdl
Frequently Asked Questions And Answers: Part 1