-- From rwdehoed@dz12.cca.rockwell.com (Russ DeHoedt)
-- Subject: Re: CRC with LFSR
-- Date: Tue, 5 Apr 94 15:08:35 GMT
-- 
-- Here's an example of an lfsr.  It's not the CRC-CCITT polynomial, but it should demonstrate
-- the general idea.  This code has been heavily edited just to "attempt" to show some lfsr stuff.
-- It has been synthesized using ASICsyn from Compass.
-- 
-- Russ,
-- 
-- lfsr.vhdl  created 04/13/93 rwd

library ieee;
use ieee.std_LOGIC_1164.all;
library compass_lib;
use compass_lib.compass.all;

entity LFSR  is
port
    (CLK       : in    std_logic;                            -- clock
     CLRF      : in    std_logic;                            -- async reset, power up
     M_FLAG    : in    std_logic;                            -- Toggle Flag; toggle indicates new cmd
     S_BLNK    : out   std_logic);                           -- pulse
end LFSR;

architecture a1 of LFSR is
 constant prop_delay:  time := 1ns;
 signal i_cnt,    n_cnt    :std_logic_vector(14 downto 1);   -- internal counter, xx.x mS pulse
 signal i_blnk,   n_blnk   :std_logic;
 signal d_mflag            :std_logic_vector(2 downto 0);    -- delayed m_flag

begin
  S_BLNK    <= i_blnk;

  sync: process(CLRF,CLK)
  begin
    if CLRF = '0'
      then i_cnt    <= "00000000000000";
           i_blnk   <= '1';
           d_mflag  <= "000";
    elsif CLK'event and CLK = '1'
      then i_cnt    <= n_cnt                         after prop_delay;
           i_blnk   <= n_blnk                        after prop_delay;
           d_mflag  <= d_mflag(1 downto 0) & M_FLAG  after prop_delay;    -- resync M_FLAG, and detect edge
    end if;
  end process;

  comb: process(d_mflag,i_cnt,i_blnk)
  begin

  -- the polynominial is from Digitial Integrated Electonics by H. Taub & D. Schilling, page 353.
  -- they use bits 14 downto 1, real designers use 13 downto 0 :)

    if    (d_mflag(2) xor d_mflag(1)) = '1'                                          
      then n_cnt <= "00000000000001";    -- restart counter
           n_blnk <= '1';
    elsif (i_cnt = "01100010110111")     -- terminial count
      then n_cnt <= "00000000000000";    -- disable counter, seq. completed
           n_blnk <= '0';                -- terminate pulse
    else n_cnt <= i_cnt(13 downto 1) & (    i_cnt(14)    -- random shift
                                        xor i_cnt(13)                      
                                        xor i_cnt(12) 
                                        xor i_cnt(2));
         n_blnk <= i_blnk;               -- continue pulse/non_pulse
    end if;
   end process;
 end;

-- 
-- ============================================       \         /
-- Russ W. De Hoedt        Phone:  319-395-3059        \   _   /        
-- Rockwell International  Fax:    319-395-4068 ________\_( )_/_________
-- E-mail: rwdehoed@dz12.cca.cr.rockwell.com           \_( o )_/        
-- ============  ASICS - R - US  ==============           \_/           
--