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VHDL SRAM models


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Currently there are two different generic simulation models available:

Both come with the following features:

The two models differ in the VHDL data types used for representation of the RAM contents. While the static memory SRAM model uses a static array of std_logic_vectors (one vector for each memory address), the dynamic memory SRAM model allocates memory dynamically whenever a memory address is written for the first time during a simulation run, thereby reducing the memory requirements of the VHDL model. Thus, use the static model only for small or densely used RAMs, while for large, sparsely used RAMs the dynamic memory model is the better choice.

The VHDL source code has successfully been compiled and simulated with Synopsys v3.3a , but uses no Synopsys-specific feature of VHDL and hence should do with any VHDL compiler/simulator which is compliant with IEEE Std 1076-1993. Some of the feedback I got on my models indicates that there is a potential problem with some VHDL simulators because their TEXTIO-package does not implement all functions as specified by IEEE Std 1076-1993, Section 14.3 .

I am always interested in receiving feedback from potential users of these VHDL models. So if you find a bug or have any questions, comments or suggestions, please feel free to send me an e-mail .

The VHDL code comes with no warranty and not all features have been tested. The files may be freely copied as long as the copyright note isn't removed from the file header. Full affiliation of anybody modifying a file shall be added to the header prior to further distribution.


André Klindworth, last change: 09.08.96