BRUSEY20(1)                                           BRUSEY20(1)


NAME
       brusey20  -  Convert  TROFF PIC state diagrams into behav-
       ioral VHDL

SYNOPSIS
       brusey20 -h

       brusey20 [ -dO ...  ] [  -sO ...   ]  [  -ve  ]  -i=infile
       -o=outfile

DESCRIPTION
       brusey20  parses  a  state diagram in TROFF PIC format and
       creates behavioral VHDL suitable for simulation  and  syn-
       thesis  by  downstream  tools.   PIC  input  is  read from
       infile, VHDL output is written to outfile, and  error  and
       any debug output is written to standard error.

OPTIONS
       -h     Print help information and quit.

       -dO    Turn on the debugging specified by O.  (See below.)

       -da    Turn all debugging on.

       -dp    Turn PIC parse debugging on.

       -df    Turn data structure fill debugging on.

       -de    Turn expression parse debugging on.

       -di    Turn I/O find debugging on.

       -dv    Turn VHDL code generation debugging on.

       -sO    Turn on synchronizing specified by O.  (See below.)

       -sr    Reset synchronously.  Not yet implemented.

       -so    If  an  output  is  Moore,  make it registered.  If
              Mealy, make it combinational.  Not yet implemented.

       -ve    Generate  Explicit  default state transitions.  Not
              yet implemented.

       -i=infile
              Read PIC input from the file named infile.

       -o=outfile
              Write VHDL output to the file named outfile.

SEE ALSO
       Thomas Clayton Mayo, Converting State Diagrams  into  Syn-
       thesizable VHDL, August, 1995.




                           26 July 1995                         1





BRUSEY20(1)                                           BRUSEY20(1)


BUGS
       The  geometric  associations  in parsing the PIC input are
       not ideal.  For example, the state name  must  be  in  the
       center  of  the  state  circle, and transition expressions
       must be within a fixed distance from the midpoint  of  the
       transition.

       Signals  in  expressions and assignments may only be logic
       type, i.e. no vectors, integers, enumerated types, etc.

       Output FSMs of registered-output Moore and  combinational-
       output Mealy types are not yet supported.

       The  output  styles  for  PICA's  VCOMP  and  VSIM and for
       Alliance have not been implemented yet.


DIAGNOSTICS
       Many.

WARNING
       brusey20 overwrites outfile without confirmation.

AUTHOR
       Tom  Mayo  N1MU  tcmayo@servtech.com































                           26 July 1995                         2