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This month we will look at the issues involved in creating a reference model in VHDL. Our primary goal in creating a reference model is to enable quick verification of the design concept. In this context it is appropriate to write the model at a level ‘beyond RTL’, a behavioural model.
Note that we are only interested in simulation of the behavioural model, we are not concerned with its synthesisability and the constraints imposed by writng an RTL model. Thus, we will still need to write a separate RTL model of the design for synthesis. Whenever design decisions need to be made at the RTL phase of the design process, we can quickly verify the validity of the decision be comparing the results of behavioural and RTL models in the same simulation environment. We do this because writing a refence model is initially quicker than writing an RTL model and because changing the RTL model is also more time-consuming. We will leave the considerations of simulating multiple models at different levels of abstraction within the same testbench for another time (this topic will probably appear on the Advanced VHDL Techniques page in the next couple of months).
So, we can really go to town using the behavioural modelling capabilities of VHDL. Or can we? Remember, we are designing a reference model for an RTL design. This means that we are constrained in developing the reference model to using the same interface as for our RTL model (yes, std_logic_vector types for our ports) as this enables comparison between the two models to be easily made during simulation. In the temporal domain, we can also make life easier by clocking the reference model in synchronisation with the RTL model, thus outputs analysis between the two models does not have to be time-skewed.
The refence model can be used for performance modelling at the bit-level. This is particularly useful for DSP-oriented designs. For example, the reference model can answer the question, is a wordlength of 24 bits sufficient for the accuracy of my DSP algorithm or do I need to go to greater wordlengths, say 32 bits. Simulating the RTL design with different wordlengths will certainly take longer, both in terms of making changes to the datapath and CPU time.
Other featues of reference models are:
For a sample reference model, visit our Model of the Month page. Here we present the reference model of a simple FIR filter. Although the reference model uses a clock, there is no architecture implied by this model - it is not an RTL description.
Oh, yes.. one last tip,
Don’t run with scissors!
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