Doulos VHDL Training, VHDL Seminar for Managers

The Doulos VHDL Management Briefing is targeted at presenting business managers with an appraisal of the issues relating to migration from traditional hardware design methods to high level design methods using VHDL. It is structured in four modules, together forming a full day presentation. A half day version is available to the client by choosing the two most appropriate modules. The four modules address different aspects of the technology and different management issues; it is anticipated that clients may wish to involve different managers or specialists on different modules. Alternative modules from the Doulos portfolio may be substituted to meet more specialised requirements. These include a more detailed presentation of the VHDL language, VHDL for system design and ESDA tools, and an introduction to the Verilog HDL.

• Making the Move...
  This module includes information gathered from organisations who have already applied high level design techniques.
• VHDL Overview
  This module presents a technical overview of the concepts behind the VHDL language. It gives an appreciation of how the language is used to model both abstraction and hardware implementation.
• Introduction to Synthesis
  How to design with VHDL for synthesis and how synthesis tools fit into the design process.
• Managing the High Level Design Process
  Practical information relating to the successful introduction and organisation of a project using high level design methods.

Target Audience
Managers or executives with budgetary responsibility; hardware design managers, team leaders and design specialists.

Comprehensive VHDL for FPGA/ASIC
Made-to-measure Training

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